Yixin Duan

*** ** **** **, *** Jose, CA *****

202-***-**** • ac80jg@r.postjobfree.com

SUMMARY

Majored n Electrical Engineering (VLSI) with strong Computer Architecture, ASIC Design, Simulation and Verification background. Experienced in ASIC Design Flow, Verilog, CDC, System Verilog, UVM, C and Linux. EDUCATION

The George Washington University, Washington, DC May 2018 Master of Science in Electrical Engineering, GPA:3.55/4.0 Relevant Courses: VLSI/ASIC Design, Simulation and Test, Electronics Devices, Microcomputer System Architecture, SoC Simulation and UVM, Big Data and Analytics, Design of Algorithm Nanjing Forestry University, Nanjing, China June 2016 Bachelor of Engineering in Electrical Engineering

TECHNICAL SKILLS

Programming Language EDA Tools Simulation Tools

Verilog Cadence- Virtuoso DSP Builder

System Verilog Synopsys- Design Vision Matlab

C Quartus II Comsol

R Low Power Solution ModelSim

Python Synopsys- Design Complier

RESEARCH PROJECTS

The George Washington University, Washington, DC Oct. 2016 – Dec. 2018 Low Power Design for 32-bit Dual-Core CPU

Programmed dual-core 5-stage pipelined processor with Hierarchy Structure in Verilog based on MIPS architecture, supporting 32-bit instruction and data width architecture.

Performed logic synthesis and generated vector file consisted of data input and scan chain trace verification (DFT), applied gate level simulation and Timing Closure.

Deployed Static Voltage Frequency Scaling (SVFS) to accomplish low power design. 8-bit TinyMIPS processor implementation

Developed an 8-bit processor with 32-bit instruction and 8-bit external memory in Verilog.

Synthesized the design and explored its power consumption and area cost in multiple operating modes.

Performed gate level simulation, inserted JTAG boundary scan and ATPG coverage analysis in TetraMax.

Generated layout with scan chain in Velocity and Virtuoso, routed the layout in Virtuoso Chip Assembly Router tool several times to remove notches.

FPGA Implementation for Real-time Ear Recognition System

Achieved reliable accuracy by implementing Altera DE-115 FPGA Board with TRDB-D5M camera.

Applied RTL design in Verilog for image extraction and recognition methods.

Designed and verified image processing including RGB to Gray, edge detection and noise deduction. Neural-based Branch Prediction model

Established neural-based branch predictor in SimpleScalar.

Compared with 2-way and combination branch predictors.

Decreased branch prediction miss rate by applying a fixed combination algorithm. 8-bit Classifier standard cell design based on neural network

Designed and implemented a classifier made of over 4000 transistors in Cadence Virtuoso, at schematic, layout level.

Performed DRC violation debugging, generated LVS report and assembled in pad-frame.

Compared 8-bit input data with original data and fixed input data continuously. Watchdog Timer Server Verification

Designed a reusable watchdog timer server, which generates a timeout signal once it fails to be reset.

Implemented UVM environment to verify the design by comparing output from a golden model. Big Data Analysis for Enron Corp email set

Performed data mining, cleaning, visualization to retrieve raw email set.

Analyzed the connection among main powerful leaders and reasons for its bankruptcy using R in Hadoop frame. WORK EXPERIENCE

Jiangsu Lianhong Automation Co., LTD, Nanjing, China June 2015 - Aug. 2015 Internship, Engineering Department

Designed multifunction power control block of low power switches based on Verilog.

Acknowledged and improved experience in the ASIC fabrication and manufacturing process.

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