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Assistant Administrative

San Jose, California, United States
November 13, 2018

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(C) 408-***-**** San Jose, CA QUALIFICATION SUMMARY

Experienced in characterization, design, Gate-level simulation, synthesis and debugging RTL Design (Verilog)

Hardware descriptive language: Verilog

Programming and Scripting Language: C, MATLAB, Python

EDA tools: Synopsys Design Compiler, Synopsys VCS tools, IC Compiler, Modelsim, HSpice, ABC, CST Microwave Studio

Microcontrollers: Arduino Uno Atmel 1522, Tiva C Series TM4C123G launch pad PROFESSIONAL EXPERIENCE

Research Assistant, Nano-Electronics and Computing Research Laboratory (NeCRL) 1/2017-8/2018 Responsibilities included simulating netlist and optimizing design of 1T1R model for RRAM technologies, comparing performance with existing PCM, STTRAM, eFuse and Antifuse, and proposing a superior model. Instructional Student Assistant, Learning Assistance Center (LAC), SFSU 9/2016-5/2018 Served in a mentoring and supervisory capacity for small groups of undergraduate students or individuals with an emphasis on providing instruction on technical subjects (Electricals circuits, Calculus, Algebra, Statistics, and Physics) in a non-technical and relatable manner. Success in improving students grades resulting in an average of 0.70 point increase in GPA. Worked as an administrative assistant to the management, conducted workshop for new tutors to ensure seamless tutoring services for the students.

Research Assistant, North South University 4/2015-12/2015 Investigated Plasmonic Solar Cell efficiency with the implementation of different types and shaped metal Nano particles. Proposed a new model which displayed 65% better performance compared to the exciting models. Intern, Yunus Center of Noble Laureate Prof. Mohammad Yunus 4/2015- 7/2015 Worked in projects to provide Solar panels to the remote areas in Bangladesh. Collecting data, preliminary planning, evaluating power consumption in each household, calculating the surface area of the solar panel needed to fulfill each house’s power consumption and cost.


M.S. in Embedded Electrical and Computer Systems GPA 3.60 8/2018 San Francisco State University, San Francisco, CA

Thesis title: Exploring and finding optimum resistive memory technologies for re-configurable logic application B.S. in Electrical and Electronics Engineering 5/2015 North South University, Dhaka, Bangladesh

Thesis title: Efficiency enhancement of Plasmonic Solar Cell with the embodiment Aluminum and Silver metal Nano Particles


Design and Characterization of 4-bit Adder (achieved the best design in terms of area and power among 12 design teams)

Designed and Implemented a 4-bit adder using Synopsys tool, HSpice, ABC, and Python ASIC Implementation and simulation of Motion Estimator from RTL to GDS

Designed and implemented the RTL for a motion estimator in 32nm CMOS using Synopsys EDA tools, and Verilog

Implemented functional verification using System Verilog through random input values and a self-checking test-bench

Generated the gate-level net-list by synthesizing the design and performed physical implementation and static timing analysis

Design of 64x32 SRAM memory cell in 90nm CMOS technology (Best design among 10 design teams)

Designed a 64x32 SRAM memory cell in 90nm CMOS Technology using Synopsys tools (Custom designer and DC Compiler) and HSpice

Implemented the Pre-layout and Post-layout simulation of the entire memory cell PUBLICATIONS

“Performance Comparison of Plasmonic Solar Cell Employing Aluminum and Silver Nano Particles”

“Electrical and Computer Engineering Laboratory Education for Female Undergraduate Students: Challenges and Solution from an Urban Perspective of Bangladesh.

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