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Union City, CA
... operating systems, JIRA, SQL, MS Project Feb 12 – Bio Architecture Lab (BAL) Berkeley, CA June 12 QA Associate BAL developed technology that transformed seaweeds into a renewable chemical to produce fuels via chemical synthesis or fermentation. ...
- 2020 May 04
Sunnyvale, CA
... Achieved the highest percent of quota (139%) Know entire design flow (RTL, Synthesis, Physical Prototyping, floor plan, timing, congestion, extraction, place & routing, verification to GDSII) and embedded software applications Provided total ...
- 2020 Apr 05
San Jose, CA
... student assignments • Co-taught with professors in industry computer applications, such as acquiring analysis and synthesis skills by teaching Excel and PowerPoint software The Grand Hotel Taipei, Taiwan Front Desk Supervisor / Front Desk Agent Dec. ...
- 2020 Mar 27
San Jose, CA
... • Organic Chemistry Synthesis Learned to synthesize many molecules like: aspirin, ethanol, pinacol. Ethanol was synthesized at 95% purity. Proficient in purification and extraction techniques (acid-base extraction, distillation, recrystallization, ...
- 2020 Mar 10
San Carlos, CA
... KIRAN HOSPITAL, INDIA DATA ANALYST JULY 2015 – MAY 2016 Balanced simultaneous requests for data analysis and synthesis compiled of multiple internal and external sources including market data, patient origin, and financial outcomes for the Health ...
- 2020 Feb 24
Saratoga, CA
... synthesis and characterization of material • Applied MATLAB to design a mathematical model to select a laminate (types of materials, number of plies and orientation) to support different in-plane loads which must satisfy Tsai-Hill failure criterion. ...
- 2020 Feb 13
Santa Clara, CA
... Synthesis RTL code to gate-level netlist by Design Compiler, then check timing issue by Prime Time. Implementing an SAT Solver June - Auguest.2018 Python, minisat Design an SAT Solver that can determine a Boolean expression is evaluated to be satis ...
- 2019 Nov 15
San Jose, CA
... Online Education and Distance Learning Cadence Design Systems, 2002 – 2013 SMCS/Architect, Invented two-stage Clock Tree Synthesis (CTS) to effectively control clock skews and minimize buffering cost Revamped the CTS algorithm to consider clock gate ...
- 2019 Sep 21
San Jose, CA
... § Languages: TCL, VHDL, C, C++, JAVA, HTML § Technical Competencies: Physical verification flow, ASIC Design Flow, FPGA Design Flow, Timing Analysis, Multiple clock domain design, RF system architecture design, RTL level design and synthesis, Test ...
- 2019 Aug 27
San Jose, CA
... EDUCATION MS: Electrical Engineering (Dec 2018) San Jose State University (CA) B.Tech: Electrical and Electronics Engineering (2012) Uttar Pradesh Technical University (India) RELEVANT COURSES Digital System Design and Synthesis, ASIC CMOS Design, ...
- 2019 May 14