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Design Engineer Engineering

Location:
San Jose, California, 95125, United States
Posted:
April 28, 2019

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Resume:

Peter Roy Ateshian

MANAGED SPECIALIST MULTI-CORPORATE MULTI-NATIONAL TEAMS OF UP TO 25 PERSONS, 3 CONTINENTS, FOR HIGH INTENSITY EXTREME VISIBILITY PROJECTS.

These included:

Multiple IP (ARM7, ARM9/ 11 Cortex, SPARC, DSP, Analog mixed signal IP cores) integration, benchmarking and SoC designs

NPS Femto Satellite redesign

Undersea LiDaR research and development

Synthesis and Scan design regression, TRW, SUN, Mentor Graphics, C, C++, OOP

200-400M Device Tape-out and silicon failure analysis (FIB) for major worldwide and domestic corporations. Mentor Graphics, AMD Memories, NVD CPLD Div., Intel ICG, Sun Microsystems, Conexant Systems, MindSpeed Technologies, Jazz Semiconductor, ARM, Ikanos Communications, LSI LOGIC.

Over 50 major projects at critical Time to Profitability. RET and OPC technology deployment at INTC, AMD since 1999.

Research in multi-hop ad hoc wireless radio and sensor networks (CISCO SYSTEMS Govt. Div. Rajant Networks).

Experience with real-time satellite ad hoc real –time bandwidth assignment (COMTECH TEL).

CMOS RSNS A/D converter design for low power micro morphing air-land UAV and Autonomous Robotic Systems.

Emergent distributed Markov chain based multi-agent operating systems.

Detailed experience with real-time embedded, C, C++, UNIX, Linux, Minix and modified Windows operating systems.

Silicon-polycrystalline Diamond new device technology advances (Sp3) for GaN & InP HEMTs.

Taught courses and completed research in ARM9 embedded control systems, SoC integration C, C++, Linux, Minix

CMOS RSNS A/D complete device design in three CMOS processes (0.35u, 0.25u, 0.18u simultaneously,

Modern operating systems, TinyOS, Minix, IOS, SoC Real Time applications

Satellite /Spacecraft communications engineering, DSP technology (BDTI).

Developed specialists for independent contracting in Integrated Circuit HLVS, OPC-HDRC, and RET.

Synthesis analysis, formal verification, debug and redesign.

IBM Agile software Development and JAVA eclipse

ADT Android malware Java forensics DARPA APAC

Software Systems Engineering RTOS/ARM for scaled autonomous systems. Agile / Scrum workflow.

C#, Microsoft. .NET project testing, verification and validation.

MatLab M, DSP, OFDM, AM, FM, QPSK, symbolic mathematics, analytic optimization, control system transfer functions, VHDL conversion to FPGA, rocket dynamic wind shear stability, analytic hierarchy process (AHP).

PROFESSIONAL EXPERIENCE

Chronological:

1992 - 2004 Exemplar Logic FPGA EDA tool box for synthesis simulation of Verilog VHDL variants. XNF and CLB with LUT optimization. Mentor Graphics Corp, Conexant MindSpeed, AMD NVD. Finite state machine,FSM design, TMR space Applications TMR design. ASIC chip CPU Data path synthesis design and timing optimization. STA timing closure. Clock tree synthesis. Side channel Attack fault injection Attack crosstalk mitigation. Oracle SPARC Intel icg missiles x86 embedded dram. Military confidential DSP analog mixed signal Applications.

2007-2012 Actel Micro Semi fusion Mixed signal FPGA DSP ARM core Applications for US Navy. Development of eBook for NPS with limited distribution.

2012 -2014 Xilinx Vivado and Intel Altera neural networks Applications for radar pattern signature recognition. Sub pixel detection of dynamic target. OpenCV and open source libraries.

2014-2015 Femto Satellite swarm network Design internet of space (IoS). Intel IDF SF presentation 2016. Laser submarine optical detection system patent application. US Navy. ARM Cortex A 9 IoT c++ QR code demonstration. REST API Azure MQTT heroku Salesforce IBM Watson Bluemix node-red arm mbed-os RTOS 5.x Cloud connectivity REST API SOAP.

2015-18 US Navy underSea Lidar imaging and laser communications. NDA and Clearances preclude disclosure. FSO laser mimo communications with machine learning compensation. NDA and Clearances preclude disclosure. IoT Analog security patent application US Navy.

Xtrm DESIGNS LLC 7/1992 - Present:

CTO / Founder /Principal

Engineering & Technical Consulting/Services Company supporting IC design, implementations and use of tape-out verification EDA tools for clients.

Naval Postgraduate School, Monterey, CA 2004 - Present

Adjunct Professor under US Navy contract to the Naval Postgraduate School, then employee 2006, responsible for CAPSTONE courses which are reviewed by ABET. 3/2004 – 09/25/2006 CCR Contractor then 09/26/2006 – present Federal Employee.

ADDITIONAL EXPERIENCE:

ICT Inc. July 1994 - March 1996

Parsec Software Dec 1993 - July 1994

Multi-Source Integration 7/1992 to 7/1994

Exemplar Logic 5/1991 to 7/1992

Silicon Design Labs /Silicon Computer Systems March 1985 - May 1991

PRIOR COMPANIES:

Atari Home Computer VLSI Design Engineer 1983-1985

EG&G Reticon Analog Design Engineer 1981-1983

Plantronics Design Engineer 1979-1981

EDUCATION:

(PhD) student Naval Postgraduate School computer science and systems engineering 2019

Master of ENGINEERING 1979 UC Berkeley (3 year program) - Combination EECS and Business Admin Dual degree Equivalent to MBA + MSc

Bachelor of Science 1976 UC Berkeley - Engineering Science- Medical Engineering

SLAC Summer Science Student - Nuclear Physics - Computational Physics Stanford Linear Accelerator Center SLAC 1974/75

University of London Passed 10 “O” Levels in one sitting 1972 (Math, Applied Math,

Physics, Chemistry, Biology, Art, Geography, French, History and English Literature) PUBLICATIONS:

2018 NAML – Supervised Learning for Mimo optical communications.

2017 DARPA SHARE Project – Femto Satellite Swarm Design

Femto Satellite Design TRNG Internet of Space presentations at Crypto/CHES 2016, ESC 2016, ARM TechCon 2016, Intel Developer Forum (IDF) 2016

Automated FPGA Trojan detection testing 2016 ITEA CYBER Workshop

Automated Testing for hardware Trojan detection 2015 IEEE SECURITY and Privacy conference

MAPLD/SEE TRNG from SEU in RAM for Space protected communications

FPGA hardware Trojan detection by differential power spectral analysis 2015 MAPLD-SEE conference

Programmable Filter Array Product - CICC 1983

AMD Non Volatile Production First Success Story 2001 (Mentor Graphics Consulting Publication)

ICT EEPLD Application Notes for Zero Power devices

ASCF - Automated Pole/Zero Z transform to Capacitor Sizes/Shapes (EG&G Reticon proprietary Software)

Application Notes for IC Design and Debug (AMD Proprietary)

DSP/SCF/Bit-slice Tradeoffs for DTMF/PSK signaling (Plantronics Proprietary)

US Citizen, languages French, Spanish from high school

REFERENCES:

Walden C Rhines CEO Mentor Graphics Corp

Rick Brown VP Micron

Gary Schottmer, VP Sp3 Inc (sp3inc.com) Mtn View

Surendra Rathur, Intel ICG San Jose

Chris Ward ARM Austin TX

Sunil Nanda ThinKit CEO/Level1 VP/Intel ICG GM

Papken DerTorossian Chairman of the Board ThermaWave

Ward Vercruysse, Intel/Oracle /SUN Microsystems

Anup Mehta, Intel/Oracle /SUN Microsystems

Uday Kapoor, Fujitsu/SUN Microsystems SPARC IP core/tools

Chin-Fu Chen, Qualcomm (ARM cores)

Ravi Ranjan, Conexant (ARM7 ARM9 cores)

Andy Brotman, Global Foundries/MindSpeed

Mark Santoro, Oracle /SUN Labs, Juniper Networks/Micro Magic CEO



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