| Resume alert | Resumes 31 - 40 of 80 |
Computer Engineering looking for internship in VLSI/ Embedded Systems
Tempe, AZ
... RTL DESIGN AND SYNTHESIS OF VARIOUS DESIGNS USING SYSTEM VERILOG Spring 2018 Designed and verified several components of a processor including Sequential Multiplier, Sequential Divider, Register File, Synchronous Read Memory and Synchronous ... - 2018 Mar 22
... RTL DESIGN AND SYNTHESIS OF VARIOUS DESIGNS USING SYSTEM VERILOG Spring 2018 Designed and verified several components of a processor including Sequential Multiplier, Sequential Divider, Register File, Synchronous Read Memory and Synchronous ... - 2018 Mar 22
Chemical Engineering
Tempe, AZ
... Skills: NMR Spectroscopy, FTIR, Dynamic Contact Angle, Surface Tension Measurements, Design of Experiments, Viscosity Analysis, Chromatography, DLS, polymer synthesis, purification techniques, pH and conductivity measurements, GPC DSC, TLC. ... - 2018 Mar 19
... Skills: NMR Spectroscopy, FTIR, Dynamic Contact Angle, Surface Tension Measurements, Design of Experiments, Viscosity Analysis, Chromatography, DLS, polymer synthesis, purification techniques, pH and conductivity measurements, GPC DSC, TLC. ... - 2018 Mar 19
Engineer Electrical Engineering
Phoenix, AZ
... • Performed backend flow from RTL code Synthesis using Tcl script to GDSII IC Layout signoff. • Implemented design using Encounter which includes Floor planning, APR and CTS. Performed STA, DRC and LVS. • Developed the hardware blocks using Simulink ... - 2018 Mar 06
... • Performed backend flow from RTL code Synthesis using Tcl script to GDSII IC Layout signoff. • Implemented design using Encounter which includes Floor planning, APR and CTS. Performed STA, DRC and LVS. • Developed the hardware blocks using Simulink ... - 2018 Mar 06
Engineering Software
Mesa, AZ
... Language, Data Structures and Algorithms, Probability and Statistics, Introduction to Software Engineering, Design and Synthesis of Digital Hardware, Embedded Microprocessor Systems, Circuits, Operating Systems, Entrepreneurship and Value Creation ... - 2018 Mar 01
... Language, Data Structures and Algorithms, Probability and Statistics, Introduction to Software Engineering, Design and Synthesis of Digital Hardware, Embedded Microprocessor Systems, Circuits, Operating Systems, Entrepreneurship and Value Creation ... - 2018 Mar 01
Engineering Data
Tempe, AZ
... Language, Data Structures and Algorithms, Probability and Statistics, Introduction to Software Engineering, Design and Synthesis of Digital Hardware, Embedded Microprocessor Systems, Circuits, Operating Systems, Entrepreneurship and Value Creation ... - 2018 Jan 24
... Language, Data Structures and Algorithms, Probability and Statistics, Introduction to Software Engineering, Design and Synthesis of Digital Hardware, Embedded Microprocessor Systems, Circuits, Operating Systems, Entrepreneurship and Value Creation ... - 2018 Jan 24
Postdoctoral Research Associate
Mesa, AZ
... assay for autoantibodies against glycoproteins 2014-2016 RESEARCH ASSISTANT - Northern Illinois University Studied synthesis and characterization of small molecule/enzyme interactions •Synthesis of small molecules as potential anti-infective ... - 2018 Jan 04
... assay for autoantibodies against glycoproteins 2014-2016 RESEARCH ASSISTANT - Northern Illinois University Studied synthesis and characterization of small molecule/enzyme interactions •Synthesis of small molecules as potential anti-infective ... - 2018 Jan 04
Design Electrical Engineering
Tempe, AZ
... - Automated RTL- Synthesis flow using TCL script. Education + Master of Science Electrical Engineering GPA: 3.6/4.0 Arizona State University, USA, May 2017 + Bachelor of Engineering in Electronics 71.25% (GPA 3.86/4.0) University of Mumbai, India, ... - 2017 Jul 26
... - Automated RTL- Synthesis flow using TCL script. Education + Master of Science Electrical Engineering GPA: 3.6/4.0 Arizona State University, USA, May 2017 + Bachelor of Engineering in Electronics 71.25% (GPA 3.86/4.0) University of Mumbai, India, ... - 2017 Jul 26
Design Electrical Engineering
Phoenix, AZ
... the same TECHNICAL SKILLS Design & Simulation Tools Cadence Design framework II (Virtuoso, Spectre), MATLAB, Calibre, RTL Synthesis HDL Verilog-A, Verilog Programming languages GNU C, Basics of Python Concepts known/Interests Operational Amplifiers ... - 2017 Jun 07
... the same TECHNICAL SKILLS Design & Simulation Tools Cadence Design framework II (Virtuoso, Spectre), MATLAB, Calibre, RTL Synthesis HDL Verilog-A, Verilog Programming languages GNU C, Basics of Python Concepts known/Interests Operational Amplifiers ... - 2017 Jun 07
Physical Design Engineer
Tempe, AZ
... Synthesis & APR (RTL-GDSII) - Convolution and Max Pooling Engine [32nm PDK] Fall 2015 Technologies: RTL-GDSII, RTL Compiler, Automatic Place and Route, Clock Tree Synthesis, Static Timing Analysis Implemented a convolution of 4x4 image with 3x3 ... - 2017 May 08
... Synthesis & APR (RTL-GDSII) - Convolution and Max Pooling Engine [32nm PDK] Fall 2015 Technologies: RTL-GDSII, RTL Compiler, Automatic Place and Route, Clock Tree Synthesis, Static Timing Analysis Implemented a convolution of 4x4 image with 3x3 ... - 2017 May 08
Six Sigma Engineer
Paradise Valley, AZ
... Materials Research Intern, IIT Kanpur May 2011 - July2011 Synthesis and Characterization of new high entropy alloys and listing the advantages over traditional alloys. CoCuFeNi, AlCoFeNi, CoCrFeNi, AlCoCuFeNi (High entropy alloys of Cobalt, Iron, ... - 2017 May 04
... Materials Research Intern, IIT Kanpur May 2011 - July2011 Synthesis and Characterization of new high entropy alloys and listing the advantages over traditional alloys. CoCuFeNi, AlCoFeNi, CoCrFeNi, AlCoCuFeNi (High entropy alloys of Cobalt, Iron, ... - 2017 May 04