Design Electrical Engineering
Resume:
ANIKET YADAV
Æ +1-480-***-**** Q ********@***.*** www.linkedin.com/in/ayadav17
***, **** ***** *****, *****, Arizona - 85282
Graduate Electrical Engineering student, adept at Physical Design, FPGA Accelerators, & Computer Architecture Concepts. Aspiring for a challenging New College Graduate position to e ciently utilize my Technical skills and Teamwork abilities. Technical Skills
+ Programming Languages: Tcl, Perl, C, MIPS, x86, Verilog, System Verilog
+ EDA & Simulation Tools: Cadence (SOC Encounter, RTL Compiler, Virtuoso, Spectre, ICFB, ELC, Abstract Generator, Layout), Synopsys(HSPICE, Hercules, SMC, StarRC, Primetime, CosmosScope, Waveviewer), Xilinx (ISE, Vivado), Modelsim, Genesis.
+ Relevant Courses: VLSI Design, Constructionist Approach To Microprocessor Design, Computer Architecture, Hardware Acceleration & FPGA Computing, System Level Design for Multi-core Architecture, SOC Verification using System Verilog
+ Other Tools & PDKs: 7nm, 28nm, 32nm, 300nm, MARS, Simple Scalar, MATLAB, Simulink, Keil, Eagle.
+ Independent Coursework: Physical design essentials: An ASIC Design Implementation Perspective, Static Timing Analysis-I Professional Experience
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Physical Design Engineer
Analog Rails, Tempe, AZ Jun 2017-Present
- Successfully synthesized NanoRisc5 SOC with Lib file generated by Digital Rails characterizer tool.
- Currently involved in Testing (finding bugs) of Newly built Characterizer, APR and STA tools.
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Teaching Assistant
Arizona State University, Tempe, AZ Oct 2016-May 2017
- Teaching Assistant for the course ’Digital Design Fundamentals’.
+
Digital Design Intern
Analog Rails, Tempe, AZ May 2016-Jul 2016
- Designed standard cell library and performed characterization of the cells.
- RTL Design and Verification with Yosis.
- Automated RTL- Synthesis flow using TCL script.
Education
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Master of Science Electrical Engineering GPA: 3.6/4.0 Arizona State University, USA, May 2017
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Bachelor of Engineering in Electronics 71.25% (GPA 3.86/4.0) University of Mumbai, India, May 2014
Academic Projects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ Synthesis and Physical Design of pipelined EDAC module for an embedded memory (Verilog, Encounter) Spring 2016
- Designed Hamming code Encoder and Decoder using Verilog.
- Performed backend flow from RTL code Synthesis using Tcl script to GDS-II IC Layout signo .
- Implemented design using Encounter which includes Floor planning, APR and CTS. Performed STA, DRC and LVS.
+ MIPS R3000 microprocessor with 5 stage pipeline (System Verilog, Perl) Fall 2016
- Designed and verified MIPS R3000 core in System Verilog with IPC of 0.7.
- Achieved CLK period of 3ns with 5 stage pipeline.
+ Characterization of E-D curves for 64 bit ALU (Vivado HLS, Sizing, VDD and Vth optimization) Spring 2017
- Characterized E-D curves for 64-bit ALU with sizing, VDD and Vth optimization using standard-cell based design flow.
- Symphony Model Compiler blocks are used to build prototype of 64 bit ALU.
- Wrote perl script to automate the process.Verified the design using generated RTL code and Test bench.
+ Custom Design of 32 word x 32 bit Register File memory bank (7nmCMOS) Spring 2016
- Design and layout of 32 entry,32 bit wide dynamic register file with one read port and one write port.
- Performed DRC and LVS, obtained parasitic extraction and performed timing analysis using HSPICE.
+ Energy-Area trade-o using architectural techniques (Vivado HLS, Xilinx Virtex7, Matrix Vector Multiplication) Spring 2017
- Prototyped two double-precision Floating-point and one fixed point MVM engines with interleaving of 4&16 using SMC blocks.
- Compared all the 3 designs for enegy and area e ciency after W, Vth and VDD optimization.
- Mapped designes into Xilinx Virtex7 to study resource utilization di erence & overhead of doing floatingpoint arithmetic.
+ Cache replacement policy using DIP, DRRIP and SHiP (Signature based Hit Predictor, Language: C) Fall 2016
- Developed a program in C to implement DIP, 2-bit DRRIP and SHiP cache replacement policy to handle data replacement on a cache miss in a Simplescalar simulator.
- Analysed performance of cache replacement policies by running number of benchmarks.
+ Performance Simulation of Alpha Processor on Simplescalar Simulator (SimpleScalar, Alpha Processor) Fall 2016
- Studied the impact of varying machine configuration i.e. Issue width, Decode width, Commit width, ROB bu er size, Load-Store queue size, Number of registers, Branch prediction scheme, local history table size on the performance of the machine for various SPEC 2006 benchmarks on SimpleScalar simulator.
- Estimated and validated the optimal configuration of parameters by analyzing the performance improvement.
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