Design Electrical Engineering

Nishranth Gauthaman

***** * **** ***** ****, Phoenix, AZ-85024 +1-480-***-**** Email: ********@***.*** My LinkedIn Profile SUMMARY

● Recent Master’s graduate in Electrical Engineering actively seeking a full-time position in Analog/Mixed Signal Circuit Design, Verification and other related areas.

● Solid understanding of Analog IC design, Data Converters, Voltage regulators, Semiconductor Device Physics and Amplifiers.

● Exhaustive hands on experience in the design and testing of analog & mixed-signal blocks at both behavioral and transistor level.

EDUCATION

M.S.E. in ELECTRICAL ENGINEERING - Arizona State University GPA: 3.14/4.0 December 2016 B.E. in ELECTRONICS & COMMUNICATION ENGINEERING - Anna University GPA: 3.7/4.0 April 2012 WORK EXPERIENCE

ANALOG IC DESIGN INTERN - Analog Rails, Tempe - AZ April 2017 - Present

● Development, simulation of several Analog and Mixed-signal IC topologies using the Analog Rails tool

● Design of various topologies of op-amps including a fully differential amplifier with gain boosting and a two stage fully differential cascoded amplifier

● Carried migration of various circuit designs from 180nm process to 65nm process using the tool and checked the performance of the tool during the same

TECHNICAL SKILLS

Design & Simulation Tools Cadence Design framework II (Virtuoso, Spectre), MATLAB, Calibre, RTL Synthesis HDL Verilog-A, Verilog

Programming languages GNU C, Basics of Python

Concepts known/Interests Operational Amplifiers (OP-AMPs), Analog & Mixed Signal design, Low Dropout Regulators

(LDOs), Bandgap References, Nyquist Rate Data Converters (Pipeline ADC, SAR ADC), DC-DC converters, PWM, Logic Design & RTL Synthesis, Biasing Circuits, Layout Design ACADEMIC PROJECTS

Design and Simulation of a 12-Bit 100MS/s Pipelined ADC [TSMC 0.18u CMOS Process, Virtuoso]

● Designed a 1.5-bit RSD stage for the first 11 stages and a 1-bit Flash ADC for the last stage

● Designed the fully differential op-amp for required DC gain and UGBW and designed a bootstrapped switch to reduce the effect of signal dependent resistance

● Measured the dynamic performance of the system in Matlab recording an SNDR of 70dB and an ENOB of 11.33 Design of a Low Dropout Voltage Regulator & Bandgap Reference [TSMC 0.35u CMOS Process, Virtuoso]

● Designed an LDO for a regulated voltage of 2.3V over a supply range of 2.5V to 3V and a load regulation of 0.1mA to 50mA

● Designed an OTA with a gain of 60dB & UGBW of 200 MHz, as a part of the control circuit that monitors and regulates the Vout through negative feedback

● Designed a 1.2V Bandgap Reference based on the Brokaw bandgap circuit to use as voltage reference Design of a DC/DC Switching Step Up Voltage Regulator [AMI 0.6u design library]

● Designed a 5 V switching voltage regulator for a line and load regulation of 1V to 4V and 0.1mA to 50mA respectively.

● Designed a comparator based PWM generator at the transistor level that operates the switch of boost converter after primary design with ideal components (VCVS, switches, etc.) Design of a 2x2 CMOS Active Photodiode Array [ON Semi 0.5u C5N design library]

● Designed the schematic and layout for a CMOS-APA for fluorescent detection (DRC, LVS)

● Used a two-stage operational amplifier with a gain of 90 dB, phase margin of 62 degrees and UGBW of 15.5 MHz (driving a 1.2 MOhm load) for converting the current from the photodiode to voltage. Design of a folded cascode amplifier with Class AB output buffer [TSMC 0.35u CMOS Process, Virtuoso]

● Designed a folded cascode op- amp with gain of 80 dB and UGBW of 60 MHz with a Phase Margin of 65 deg and a Gain Margin 31 dB.

● Achieved a slew rate of 10 V / μs with a load of 1pF had a Input Referred Noise of 8.091 nV/sqrt(Hz) and consumed a max power of 1.65 mW using a 3V power supply.

Modelling of RSD-based 1.5-bit per Stage Pipelined ADC using [MATLAB]

● Developed a model of N-Bit, RSD-based 1.5-bit per stage pipelined ADC using MATLAB and modelled the effects of DC gain, Capacitor Mismatch for generic values of reference voltage.

● Verified the correct operation of the model by simulating it across DC Gain and Capacitor Mismatch scenarios.

● Plotted DNL, INL and the Capacitor mismatch ratio Vs SNDR & ENOB Image Convolution and Max-pooling ASIC module design [Synopsys iPDK 32nm, Virtuoso]

● Designed the behavioral model in Verilog and verified the design with the testbench.

● Synthesized the behavioral model to gate level with the Cadence RTL compiler tool and layout the design over a floor plan with the Cadence Encounter tool ensuring no DRC and LVS violations

● Carried out Post Layout timing and power analysis using PrimeTime tool. RELATED COURSEWORK

1. Analog Integrated Circuits

2. Advanced Analog Integrated Circuits

3. Nyquist Rate ADCs

4. VLSI Modulation Circuits

5. Low Power Bioelectronics

6. VLSI Design

PAST EXPERIENCE

SENIOR SYSTEM EXECUTIVE - Cognizant Technology Solutions, Bangalore, India September 2012 - December 2014

● Involved in access management on Windows & Linux server environments and directly handled/resolved problems faced by users

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