| Resume alert | Resumes 61 - 70 of 80 |
Design Electrical Engineer
Tempe, AZ
... * Experience in ASIC flow and Digital design, including: RTL coding, Simulation, Functional verification and Synthesis. * Familiarity with software design, control systems and manufacturing processes. * Strong knowledge of Verilog with logic design ... - 2013 Jan 28
... * Experience in ASIC flow and Digital design, including: RTL coding, Simulation, Functional verification and Synthesis. * Familiarity with software design, control systems and manufacturing processes. * Strong knowledge of Verilog with logic design ... - 2013 Jan 28
Information Technology High School
Tempe, AZ
... Student knowledge and skills are enhanced through highly engaging, intensive, long-term contact with research scientists, engineers, mathematicians and project leaders who help the students use innovative technologies in a new synthesis of online ... - 2013 Jan 23
... Student knowledge and skills are enhanced through highly engaging, intensive, long-term contact with research scientists, engineers, mathematicians and project leaders who help the students use innovative technologies in a new synthesis of online ... - 2013 Jan 23
Training Computer
Tempe, AZ
... International Symposium on Visual Computing (ISVC) 2010, Las Vegas, NV [8] Jin Zhou, Qiang Zhang, Baoxin Li and Ananya Das, Synthesis of Stereoscopic Views from Monocular Endoscopic Videos, IEEE Computer Vision and Pattern Recognition (CVPR) 2010 ... - 2012 Dec 14
... International Symposium on Visual Computing (ISVC) 2010, Las Vegas, NV [8] Jin Zhou, Qiang Zhang, Baoxin Li and Ananya Das, Synthesis of Stereoscopic Views from Monocular Endoscopic Videos, IEEE Computer Vision and Pattern Recognition (CVPR) 2010 ... - 2012 Dec 14
Computer Science Planning
Tempe, AZ
... Tempe, AZ 85287 Office:480-***-**** Home:480-***-**** Email:abpgy9@r.postjobfree.com :http://rakaposhi.eas.asu.edu/rao.html ResearchInterests Automated Planning (AI):Plan Synthesis in metric, temporal, partially accessible and stochas- tic worlds. ... - 2012 Nov 04
... Tempe, AZ 85287 Office:480-***-**** Home:480-***-**** Email:abpgy9@r.postjobfree.com :http://rakaposhi.eas.asu.edu/rao.html ResearchInterests Automated Planning (AI):Plan Synthesis in metric, temporal, partially accessible and stochas- tic worlds. ... - 2012 Nov 04
Electrical Engineer Manager
Phoenix, AZ
... Design I Synopsys Corporation 2002 to 2007 Integrated Circuit Physical Design II Synopsys Corporation 2003 to 2007 Clock Tree Synthesis Synopsys Corporation 2004 to 2007 Rail Analysis and Design Synopsys Corporation 2006 to 2007 Hierarchical Design ... - 2012 Oct 16
... Design I Synopsys Corporation 2002 to 2007 Integrated Circuit Physical Design II Synopsys Corporation 2003 to 2007 Clock Tree Synthesis Synopsys Corporation 2004 to 2007 Rail Analysis and Design Synopsys Corporation 2006 to 2007 Hierarchical Design ... - 2012 Oct 16
Assistant State University
Mesa, AZ, 85204
... Jan 2011 - July 2011 Research Associate, Strauss Research Group Colorado State University, Fort Collins, CO Responsibilities -Synthesis and analysis of new ferrocene derivative compounds -- -Product analysis using most suitable analytical methods ... - 2012 Sep 20
... Jan 2011 - July 2011 Research Associate, Strauss Research Group Colorado State University, Fort Collins, CO Responsibilities -Synthesis and analysis of new ferrocene derivative compounds -- -Product analysis using most suitable analytical methods ... - 2012 Sep 20
Design Engineer
Tempe, AZ, 85281
... • Traffic Light Design: Creating a Button Handler module that will create useable signals to illustrate user I/O and Finite-State-Machine design that Design of a traffic light control and seven segment module on Xilinx Spartan-3 FPGA and synthesis ... - 2012 Apr 21
... • Traffic Light Design: Creating a Button Handler module that will create useable signals to illustrate user I/O and Finite-State-Machine design that Design of a traffic light control and seven segment module on Xilinx Spartan-3 FPGA and synthesis ... - 2012 Apr 21
Design Mechanical Engineering
Tempe, AZ, 85281
... Selected for Computational design synthesis summer camp (TU Munich, August 2011) WORKSHOPS ATTENDED 1. ‘Mechanical engineering Design knowledge modeling’ (Organized by Georgia Institute of Technology, ASME IDETC 2011) 2. ‘Pneumatic and Electrical ... - 2011 Nov 07
... Selected for Computational design synthesis summer camp (TU Munich, August 2011) WORKSHOPS ATTENDED 1. ‘Mechanical engineering Design knowledge modeling’ (Organized by Georgia Institute of Technology, ASME IDETC 2011) 2. ‘Pneumatic and Electrical ... - 2011 Nov 07
Engineer Design
Tempe, AZ, 85283
... Experience with hardware design, GLS simulations, synthesis and all aspects of DFT . Strong knowledge in SOC testbenches creation and system level simulations . Proven ability to improve test coverage of system on chip . Extensive experience of scan ... - 2010 Nov 01
... Experience with hardware design, GLS simulations, synthesis and all aspects of DFT . Strong knowledge in SOC testbenches creation and system level simulations . Proven ability to improve test coverage of system on chip . Extensive experience of scan ... - 2010 Nov 01
Engineer Design
Chandler, AZ, 85226
... Design flows encompass Verilog netlist input, block or full chip floor planning, Design constraints input, Auto Placement, Placement Optimization, Clock Tree Synthesis, Clock Tree Optimization, Static Timing Analysis, Fixing Timing Violations, ... - 2010 Oct 12
... Design flows encompass Verilog netlist input, block or full chip floor planning, Design constraints input, Auto Placement, Placement Optimization, Clock Tree Synthesis, Clock Tree Optimization, Static Timing Analysis, Fixing Timing Violations, ... - 2010 Oct 12