Saketharam Venkataramanan

Tempe, AZ • 480-***-**** • acz64w@r.postjobfree.com • www.linkedin.com/in/saketharamv

Qualifications Profile

Master of Science Graduate with extensive education, research, and Digital ASIC and SOC Design experience, as well as a passion for pursuing Electrical Engineering roles that can contribute to leading edge innovations in business and technology.

Skilled SOC Design Engineer with expertise in Digital Logic Design, ASIC Design Flow, RTL-GDSII Design & Verification, and Physical Design (14nm FinFET, 32nm).

Core Technologies:

Languages :

Verilog, System Verilog, Verilog-A, Python, C/C++, Tcl, Shell Scripting, MATLAB R2015b

Tools :

Cadence Encounter RTL Compiler, Cadence - Virtuoso Schematic & Layout Suite (DRC & LVS), Synopsys – Primetime, Synopsys - Hercules, Mentor Graphics - ModelSim, Spectre Circuit Simulator, HSPICE, StarRC, Silvaco – Atlas, Athena, HSPICE.

Educational Background

Master of Science in Electrical Engineering – 12/2016

Arizona State University, Tempe, Arizona GPA 3.25

Courses: VLSI Design, Digital Circuits, Computer Architecture, Analog IC, Semiconductor Memory Technologies,

VLSI Modulation Ckts., Advanced Analog IC, Solid State Devices, Semiconductor Device & Process Simulation.

Bachelor of Electronics and Communications Engineering – 8/2014

Valliammai Engineering College, Tamil Nadu, India GPA 3.32

Courses: VLSI Design, Microprocessors, Linear Integrated Circuits, Computer Architecture, Embedded Systems.

Work Experience

Analog Rails, Tempe, Arizona

IC Design Engineer, Intern April 2017 – Present

Technologies: 14nm FinFETs, 180nm Bulk CMOS

Designing layouts for Standard Cell Library in 14nm FinFETs, and 180nm Bulk CMOS technologies.

Characterizing the Standard Cell Library by creating models for delay, function, constraints, and power.

Developing RTL codes for digital designs, and developing scripts to synthesize using YOSYS for Physical Design Verification & Validation using Testbench.

Extracting parasitic capacitance, IR drop, Electron Migration from the Physical Design.

Independently developing scripts and design methodologies for Configuration files, and Liberty Timing files for characterization of timing and power for the Combinational and Sequential circuits.

Academic Projects

Arizona State University, Tempe, Arizona

Graduate Student, Electrical Engineering, 2015 – 2016

Impact of Channel Doping Concentration on 25nm Double-Gate MOSFET Fall 2016

Technologies: Silvaco – Atlas, Athena

Presented a paper on the effects of doping concentration of channel on 25nm DG-MOSFET.

Modelled 25nm vertical DG-MOSFET device using Silvaco-Atlas successfully.

Analyzed quantum effects of scaling on I-V characteristics, electron mobility, and presented the results

Proposed trade-offs between doping and operation, and devices with High-K dielectrics.

Technology Scaling of Fully Depleted SOI MOSFET Fall 2016

Technologies: Silvaco – Atlas, Athena

Successfully modelled 180, 120, 90, 45, and 25nm FDSOI MOSFETs.

Designed & simulated submicron MOSFETs with decreasing device lengths to study its properties

Obtained I-V & device output characteristics for non-isothermal conditions

Custom Standard Cell Library Design and Characterization [32nm PDK] Spring 2016

Technologies: SAED, 32nm PDK, Cadence – Virtuoso Schematic & Layout Suite

Building on two highly successfully years of graduate level innovation and design, this ambitious project yielded a library of working combinational cells and logic gates.

Successfully designed a functioning library of standard cells using Encounter Library Characterization (ELC)

Validated and optimized NAND, NOR, INV, AOI, XOR, XNOR, DFFARS, Buffers to have minimum delay and area following standard cell rules.

Synthesis & APR (RTL-GDSII) - Convolution and Max Pooling Engine [32nm PDK] Fall 2015

Technologies: RTL-GDSII, RTL Compiler, Automatic Place and Route, Clock Tree Synthesis, Static Timing Analysis

Implemented a convolution of 4x4 image with 3x3 kernel design using RTL Verilog code in ModelSim.

Achieved an updated optimized design by applying a Pipelined Modified Booth Algorithm, and a successfully reduced 70% of core area, power use, and latency.

Improved design with Static Timing Analysis (STA) and Power Analysis was done with Synopsis Primetime.

Custom Designed 32 X 32 Dynamic Register File [32nm PDK] Fall 2015

Routing Strategy: Manhattan Routing

Achieved successful design of a 32X32 bit dynamic register file, with one read, one write port and circuiting that ensured R/O operation.

Markedly reduced power use, improved SF process corner metrics, and minimized EDP.

Synthesis & APR (ASIC Design Flow) – 2-Bit Adder [32nm PDK] Fall 2015

Technologies: ASIC Design Flow, Cadence RTL Compiler, APR, Cadence Encounter 14.2, Synopsis Primetime.

Deftly managed RTL Verilog code using ModelSim to produce functioning 2-bit adder.

Image Convolution & Max Pooling Algorithm Project Using Python Spring 2015

Technologies: Python

Built operational convolution and max-pooling module with 4x4 pixel image and 3x3 convolution kernel

Achieved extraction of matrix values from images by performing convolution on the image to extract values, then converted values back to image to show the processing.

Design of 8-Bit modulo Adder [32nm PDK] Spring 2015

Technologies: Cadence Virtuoso – DRC, LVS, StarRC Extraction

Created 8-bit Modulo Adder by implementing True Single Phase Clocking to develop Full Adder and D-Flip Flop.

Successfully optimized area by administering EDP of the design.

University Employment Experience

Teacher’s Aide / Grader: Dept. of ECEE, Arizona State University, Tempe, AZ Aug 2016 - Dec 2016

Responsible for grading the works of Graduate and Undergraduate students of Solid State Devices class under Prof. Yu Yao, for Fall 2016 semester.

Assisted the professor in preparing the solutions for quizzes, exams, and assignments in the course.

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