email@example.com • 480-***-**** • https://www.linkedin.com/in/akhil-veeranala
Graduate student in Electrical Engineering actively looking for full time opportunities in Analog, Digital/Mixed- Signal Design domain beginning Dec 2017. I worked as a systems engineer for 1.5 years which helped me hone my analytical and problem-solving skills.
Master of Science in Electrical Engineering Dec 2017 Arizona State University GPA:(3.5/4)
Bachelor of Engineering in Electronics and Communication engineering April 2014 Acharya Nagarjuna University GPA:(3.4/4)
Programming Languages C, C++, PERL.
HDL/HVL Verilog, System Verilog.
Simulation Tools Cadence, Spectre, Matlab, Hspice, Simulink, Vivado, Cadence Encounter, GENESIS2. Layout Tools Cadence Virtuoso Layout Editor. [Nodes: 7nm,28nm,32nm, 180nm, 500nm]. LVS/DRC Tools Calibre, Hercules.
Product Engineer Intern: ON Semiconductor, San Jose, CA Oct 2017 – Dec 2017
• Working on Validation of Image sensors on both wafers and packaged parts; Failure Analysis of Image Processors.
• Failure analysis of sensors by the ATE testers and Physical analysis of the die to narrow down the faults in the chip.
• Electrical and Image Characterization of failures and finding out the cause of the failures.
• Providing characterization support for fabrication process improvements by Post Silicon validation of image sensors. Tutor: C, C++ Arizona State University, Tempe, Arizona Aug 2016 – Sep 2017 Systems Engineer: Infosys Ltd, Hyderabad, India May 2014 – Oct 2015
• Knowledge gained on C, C++, HTML and Operating Systems. PROJECT WORK
MIPS R3000 microprocessor design with 5 stage bypass pipeline (System Verilog, Perl) Spring 2017
• Designed and verified MIPS R3000 core in System Verilog with an IPC of 0.9.
• Achieved a CLK period of 3ns with 5 stage bypass pipeline. Hardware Acceleration of Lightweight Encryption (“Simon”) Engine (Simulink, Matlab, Verilog, Vivado) Spring 2017
• Designed Simon block cipher engine using Verilog.
• Performed backend flow from RTL code Synthesis using Tcl script to GDSII IC Layout signoff.
• Implemented design using Encounter which includes Floor planning, APR and CTS. Performed STA, DRC and LVS.
• Developed the hardware blocks using Simulink and synthesized using Synphony Model Complier. Mapped the design to a Xilinx Virtex7 FPGA target. Area consumed and the timing requirements are checked using Vivado. Design of SRAM, RF, Sequential Multiplier and Divider modules (Genesis2, System Verilog, Perl) Spring 2017
• Implemented using behavioral modelling. Handshake signals were utilized to represent the finite state machine. Implemented all the logics using Verilog and PERL. All the logics were parameterized.
• Timing Slack, Power consumption and area is measured. Designed to work for 2ns. Design of 16 16 RF with 1 write and read port (Cadence6, 7nm FinFET PDK: http://asap.asu.edu/) Fall 2016
• Design a 4:16 decoder with predecode and post decode stages for selecting 16 word lines in the SRAM cells.
• Integrating all the building blocks to design the final 16 16 register file and performing post-layout signoff checks like DRC, LVS, Static Timing Analysis (STA). Extracting the parasitics (pex netlist) from the layout.
• Simulating the pex netlist using HSPICE to determine the read delay and write delay. Standard Cell Library & 8 bit Modulo Adder Design on a 32nm PDK technology (Cadence6) Spring 2016
• Created standard cells for NANDX2, NORX3, NANDX3; Created cell for 8-bit Modulo Adder.
• The design is performed using Cadence 6 for the generation of schematic & layout. Performed DRC & LVS checks.
• Generated netlists and verified using HSPICE. Optimization of Energy-Delay Product(EDP) and Layout area. Evaluate the affects of cache on performance on microprocessors using Simple Scalar simulator (Language: C) Fall 2016
• Developed a program in C to implement DIP, DRRIP and SRRIP cache replacement policies to handle data replacement on a cache miss in a Simplescalar simulator
• Analyzed performance of cache replacement policies by running number of benchmarks.