| Resume alert | Resumes 1 - 10 of 80 |
Electrical Engineering Mixed Signal
Tempe, AZ
... purposes using SystemVerilog (current project) Working with two other people, using System Verilog, we are implementing a 16-point FFT OVA algorithm and testing the speed of the algorithm in a pre-layout chip using DC compiler synthesis tool. ... - Mar 19
... purposes using SystemVerilog (current project) Working with two other people, using System Verilog, we are implementing a 16-point FFT OVA algorithm and testing the speed of the algorithm in a pre-layout chip using DC compiler synthesis tool. ... - Mar 19
Class A Cdl Driver
Phoenix, AZ
... Major graphic design/architect Related Courses: interior design, architecture design Activities: *study architectural analysis, architectural synthesis, and architectural evaluation Workshops and Training CDL Training Program. October 2023 - ... - Jan 17
... Major graphic design/architect Related Courses: interior design, architecture design Activities: *study architectural analysis, architectural synthesis, and architectural evaluation Workshops and Training CDL Training Program. October 2023 - ... - Jan 17
Los Angeles Early Childhood
Mesa, AZ
... I emphasize writing to support synthesis of written text and logical development of specific writing goals. ENG 091: Developmental Writing (1section) Placement English course to develop grammar, sentence structure, and paragraph development skills ... - 2023 Dec 13
... I emphasize writing to support synthesis of written text and logical development of specific writing goals. ENG 091: Developmental Writing (1section) Placement English course to develop grammar, sentence structure, and paragraph development skills ... - 2023 Dec 13
Verilog, Python, C/C++
Phoenix, AZ, 85003
... Employed Synopsys Design Compiler for the synthesis of RTL (Register Transfer Level) descriptions into gate-level representations. Conducted extensive simulations and analyses using Mentor Graphics ModelSim to evaluate the performance and efficiency ... - 2023 Nov 17
... Employed Synopsys Design Compiler for the synthesis of RTL (Register Transfer Level) descriptions into gate-level representations. Conducted extensive simulations and analyses using Mentor Graphics ModelSim to evaluate the performance and efficiency ... - 2023 Nov 17
Health Sciences Clinical Research
Phoenix, AZ
... “Ketone-based Cholesterol Synthesis is Significantly Altered in Young Adult APOE ε4 Carriers.” Midwestern University, Glendale, AZ. Dr. Kenneth A. Suarez Research Day. “Young Adult Carriers of the Alzheimer's Disease Risk Factor APOE4 Show Broad ... - 2023 Oct 26
... “Ketone-based Cholesterol Synthesis is Significantly Altered in Young Adult APOE ε4 Carriers.” Midwestern University, Glendale, AZ. Dr. Kenneth A. Suarez Research Day. “Young Adult Carriers of the Alzheimer's Disease Risk Factor APOE4 Show Broad ... - 2023 Oct 26
Summer Intern Process Engineer
Chandler, AZ
... Applied vapor phase synthesis and doping of monolayer MoS2(Molybdenum disulfide) Cleanroom work experience Worked with team that assembled, installed, and managed furnace in cleanroom and lab. Industrial Risk Management Trainee (Boot Camp) February ... - 2023 May 25
... Applied vapor phase synthesis and doping of monolayer MoS2(Molybdenum disulfide) Cleanroom work experience Worked with team that assembled, installed, and managed furnace in cleanroom and lab. Industrial Risk Management Trainee (Boot Camp) February ... - 2023 May 25
Engineer Intern Electrical Engineering
Tempe, AZ
... Design, synthesis, and layout of 2bit Adder using APR (Cadence Innovus,7nm PDK FinFET) Fall 2022 • RTL Code and simulation using ModelSim and synthesized using Design Compiler, generated Timing, Area, and Power reports. Performed floor and power ... - 2023 May 21
... Design, synthesis, and layout of 2bit Adder using APR (Cadence Innovus,7nm PDK FinFET) Fall 2022 • RTL Code and simulation using ModelSim and synthesized using Design Compiler, generated Timing, Area, and Power reports. Performed floor and power ... - 2023 May 21
Summer Intern Process Engineer
Chandler, AZ
... Applied vapor phase synthesis and doping of monolayer MoS2(Molybdenum disulfide) Cleanroom work experience Worked with team that assembled, installed, and managed furnace in cleanroom and lab. Industrial Risk Management Trainee (Boot Camp) February ... - 2023 May 21
... Applied vapor phase synthesis and doping of monolayer MoS2(Molybdenum disulfide) Cleanroom work experience Worked with team that assembled, installed, and managed furnace in cleanroom and lab. Industrial Risk Management Trainee (Boot Camp) February ... - 2023 May 21
Cloud Software Engineer
Phoenix, AZ
... Algorithms and Data Structures: MaxMSP music synthesis and analysis, robot control, machine learning, OCR, pathfinding, 3D graphics and raytracing, operating systems Continuous Integration Testing: Jenkins, TravisCI, CircleCI, GitHub Actions Other: ... - 2023 Mar 27
... Algorithms and Data Structures: MaxMSP music synthesis and analysis, robot control, machine learning, OCR, pathfinding, 3D graphics and raytracing, operating systems Continuous Integration Testing: Jenkins, TravisCI, CircleCI, GitHub Actions Other: ... - 2023 Mar 27
Design Intern Research Associate
Tempe, AZ
... Development Skills: Floor-planning, placement, clock tree synthesis and routing, setup, and hold, HSPICE, CMOS, ARTS. Hardware/Tools/OS: Cadence Virtuoso, Innovus, Synopsys Design Compiler, Primetime, ModelSim, Calibre (DRC, LVS, Pex), MAT- LAB ... - 2023 Mar 21
... Development Skills: Floor-planning, placement, clock tree synthesis and routing, setup, and hold, HSPICE, CMOS, ARTS. Hardware/Tools/OS: Cadence Virtuoso, Innovus, Synopsys Design Compiler, Primetime, ModelSim, Calibre (DRC, LVS, Pex), MAT- LAB ... - 2023 Mar 21