Sharayu Acharya

ac4wfz@r.postjobfree.com +1-480-***-**** LinkedIn: sharayu-acharya

Computer Engineering Graduate Student with focus on VLSI Design, Architecture & Embedded Systems looking for Summer'18 internship. EDUCATION

Ira Fulton School of Engineering, Arizona State University, Tempe, Arizona, USA May 2019 Master of Science in Computer Engineering (Electrical Engineering) with GPA 3.13/4 University of Mumbai, India May 2015

Bachelor of Engineering in Electronics Engineering with distinction. RELEVANT COURSEWORK

Master’s Courses: Embedded Systems Programming, Digital Systems and Circuits, Constructionist Approach to Microprocessor Design, Hardware Acceleration and FPGA Computing.

Undergrad Courses: Embedded Systems and Real Time Programming, Computer Programming, VLSI Design, Digital System Design, Communication Systems and Applications Communication Networks. TECHNICAL SKILLS

Hardware Description Languages: Verilog HDL, System Verilog, VHDL. Scripting/Programming Languages: Python, PERL, C/C++, T-SQL, Java Operating Systems: Linux, Windows

Software: Cadence Virtuoso, MATLAB Simulink, Xilinx Vivado Design Suite System Edition, Mentor Graphics ModelSim Synopsys Synphony Model Compiler, Design Compiler, Synplify Pro, HSPICE, Visual Studio 2012 - MSDN, SQL Server Management Studio

(SSMS), MATLAB, Eclipse, Vijeo Citect, PCB Wizard, Unity ProXL Training: Industrial Automation Training on PLC & SCADA, Godrej & Boyce PROFESSIONAL EXPERIENCE

Tata Consultancy Services Assistant Systems Engineer Mumbai, India September 2015 - June 2017 Role: T-SQL and SQL Server Reporting Services (SSRS) DevOps Engineer.

• Handled real-time support for clients spanning 7 countries.

• Met a record deadline of few months by taking initiative single headedly to deliver the regulatory reports and aftercare for South Korea Branch which helped the company retain the client for future projects due to the quick turnaround shown. Larsen & Toubro

Technology & Product Development Centre Intern Mumbai, India Nov 2013 – Dec 2013 Collaborated with the research and technology development team to use cutting edge technologies, develop Bill of Material, test instructions, setup, procedure and equipments for testing and validation. With strong communication & negotiation skills components were delivered well in time.

Defence Electronics Department Intern Mumbai, India June 2013 – July 2013 Designed and implemented PCB for different controller cards, fabricated and delivered product. ACADEMIC PROJECTS

1. RTL DESIGN AND SYNTHESIS OF VARIOUS DESIGNS USING SYSTEM VERILOG Spring 2018 Designed and verified several components of a processor including Sequential Multiplier, Sequential Divider, Register File, Synchronous Read Memory and Synchronous/Asynchronous FIFO. Synthesized the designs using Synopsys DC Compiler to generate gate level hardware on 32nm Technology Node. 2. ASIC DESIGN OF 16-1 INTEGRATE AND FIRE NEURON Fall 2017 Designed full adders; 4bit, 5bit, 6bit,7bit, OR gates, D FF and layout of neuron. The layout was designed using CADENCE Virtuoso 32nm PDK and simulated using HSPICE. Architecture focused on high performance and minimum delay. 3. DISTANCE CONTROLLED ANIMATION VIA SPI BUS ON INTEL GALILEO GEN II Fall 2017 Linux user application to use spidev to send the SPI messages to display (MAX7219) and use gpiolib to trigger and measure distance from the sensor. Developed a Linux device driver for SPI based display(MAX7219) to generate patterns on the LED Matrix using IOCTL command and another Linux device pulse measurement driver to measure distance with an Ultrasonic sensor using Interrupt Service Routine and Time Stamp Counter.

4. GPIO CONTROL IN LINUX Fall 2017

Programmed a user-level and kernel module for GPIO controls via the interface of GPIO core using pin multiplexing mechanism to control intensity & the combination of RGB colors and terminate on double click of mouse button using file operations like open, write, IOCTL and release.

5. PLC BASED CONVEYOR BELT PROCESS CONTROL

B.E. Project at Larsen & Toubro (Control & Automation) Fall 2014– Spring 2015 Implemented a real-time conveyor belt application using PLC Simulator Software (Vijeo Citect) on Siemens PLC with 100 digital inputs, 20 analog inputs and 50 digital outputs. Developed logic using function block diagram for 2 types of conveyors i.e. High Tension & Low Tension Conveyors, a group block, flap gate, metal detector and magnetic separator. Suggested remedies for the challenges faced during interfacing PLC.