| Resume alert | Resumes 61 - 70 of 412 |
FAE
Vasant Nagar, Karnataka, India
... TECHNICAL EXPERTISE • Design, Development and Testing of hardware-based boards for Defense & Aerospace applications based on Micro controller, FPGA and CPLD’s. • Expertise in Hardware Testing (ATP), Functional Testing of boards (FTP), Integration ... - 2019 Jul 28
... TECHNICAL EXPERTISE • Design, Development and Testing of hardware-based boards for Defense & Aerospace applications based on Micro controller, FPGA and CPLD’s. • Expertise in Hardware Testing (ATP), Functional Testing of boards (FTP), Integration ... - 2019 Jul 28
Good knowledge in C/C++.
Bangalore, Karnataka, India
... Language : C Platform : Windows 7/XP/8/10 using 8051 microcontroller Description The scope of the project was to design, develop and implementation of an efficient hardware architecture for VGA monitor controllers based on FPGA technology. The ... - 2019 Jul 20
... Language : C Platform : Windows 7/XP/8/10 using 8051 microcontroller Description The scope of the project was to design, develop and implementation of an efficient hardware architecture for VGA monitor controllers based on FPGA technology. The ... - 2019 Jul 20
Design Engineering
Vasant Nagar, Karnataka, India
... Pincode-560083 Mobile: +91-954******* LinkedIn ID: https://www.linkedin.com/in/manibhargav-ogirala-23a518172/ Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Jul 12
... Pincode-560083 Mobile: +91-954******* LinkedIn ID: https://www.linkedin.com/in/manibhargav-ogirala-23a518172/ Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Jul 12
Verilog, System Verilog, UVM, SOC Verification, ASIC Verification
Vasant Nagar, Karnataka, India
... • FPGA generic and specific code (Xilinx & Altera) for memory, clock adaption and JTAG tap. • System configuration in a single definition file. • Example firmware’s using UART and Ethernet. • Test bench included, simulating target software and ... - 2019 Jul 08
... • FPGA generic and specific code (Xilinx & Altera) for memory, clock adaption and JTAG tap. • System configuration in a single definition file. • Example firmware’s using UART and Ethernet. • Test bench included, simulating target software and ... - 2019 Jul 08
Engineer Design
Karnataka, India
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17
Engineering Design
Vasant Nagar, Karnataka, India
... SUMMARY OF QUALIFICATIONS: Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using ... - 2019 Apr 19
... SUMMARY OF QUALIFICATIONS: Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using ... - 2019 Apr 19
Power Electrical
Vasant Nagar, Karnataka, India
... Description: Application of the Msp430 in place of FPGA to control the power requirements of a satellite. Centre: ISRO, U.R. Rao Satellite Centre. Achievements: Cleared GATE exam 2019 with a score of 414. Obtained an overall percentile of 81.68 in ... - 2019 Apr 16
... Description: Application of the Msp430 in place of FPGA to control the power requirements of a satellite. Centre: ISRO, U.R. Rao Satellite Centre. Achievements: Cleared GATE exam 2019 with a score of 414. Obtained an overall percentile of 81.68 in ... - 2019 Apr 16
Design Engineering
Vasant Nagar, Karnataka, India
... 10th cross #1/1, Mobile: +91-886******* Kothnur Post, Bengaluru-560077 LinkedIn ID ac81zv@r.postjobfree.com Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Apr 10
... 10th cross #1/1, Mobile: +91-886******* Kothnur Post, Bengaluru-560077 LinkedIn ID ac81zv@r.postjobfree.com Summary of Qualifications Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. ... - 2019 Apr 10
Design Verification Engineer
Vasant Nagar, Karnataka, India
... VLSI Domain Skills: • HDL : Verilog • HVL : SystemVerilog • Verification Methodology : Coverage Driven Verification • TB Methodology : UVM • Protocols : SPI • EDA Tools : Riviera Pro – Aldec, ISE – Xilinx • Domain : ASIC/FPGA front-end Design and ... - 2019 Apr 05
... VLSI Domain Skills: • HDL : Verilog • HVL : SystemVerilog • Verification Methodology : Coverage Driven Verification • TB Methodology : UVM • Protocols : SPI • EDA Tools : Riviera Pro – Aldec, ISE – Xilinx • Domain : ASIC/FPGA front-end Design and ... - 2019 Apr 05
Training Design
Bangalore, Karnataka, India
RAMAYANAMTHARUNKUMAR MailId:tharun******@ac8ofy@r.postjobfree.com Mobileno:+91-773******* B.Tech(ECE) SkillSet HDLs Hardware Scripting Programming Tools Language Verilog, ZedBoard, TCL(basic) C(basic) QuestaSim, FPGA,SV Xilinx7series Vivado FPGA ... - 2019 Mar 05
RAMAYANAMTHARUNKUMAR MailId:tharun******@ac8ofy@r.postjobfree.com Mobileno:+91-773******* B.Tech(ECE) SkillSet HDLs Hardware Scripting Programming Tools Language Verilog, ZedBoard, TCL(basic) C(basic) QuestaSim, FPGA,SV Xilinx7series Vivado FPGA ... - 2019 Mar 05