Engineer Design

PRASANNA KUMAR H M

BTM *st stage, Bangalore, ****29 91+827******* *****************@*****.***

Career Objective

Looking for an opportunity where I can showcase my skills and talent which would help to develop myself and the organization.

I want to turn every work assigned by organization as an opportunity to build myself. Education

QUALIFICATION

SCHOOL/COLLEGE

BOARD/UNIVERSITY

YEAR OF

PASSING

PERCENTAGE

B.E

(ECE)

Jain Institute Of

Technology,

Davangere

Visveswaraiah

Technological

University,

Belagavi

2018

67.80

XII

(PCMB)

Smt. Pushpa

shamanur

mahalingappa pre-

university college,

Davanagere.

Department Of Pre-

University

Education

Karnataka

2014

76.17

X Sri morarji desai

model residential

school, kerebilachi

Karnataka Secondary

Education Exam Board

2012

71.04

Technical Skills

C PROGRAMMING

Basic knowledge on Data structure and Algorithms. VLSI

Good understanding of the ASIC and FPGA design flow

Extensive experience in writing RTL models using Verilog HDL.

Good experience in writing Test benches using SystemVerilog and UVM

Very good knowledge in verification methodologies TOOLS

QuestaSim : Mentor Graphics

Riviera Pro : Aldec

ISE : Xilinx

Work Experience

Currently undergoing hands-on technical training program on Advanced VLSI Design and Verification at Maven silicon VLSI Design and Training Center, Bengalore. Personal Attributes

Quick learning of new initiatives

Ability to work effectively under pressure

Ability to meet deadlines through effective time management

Maintaining healthy interpersonal relationships with team Projects Details

TITLE Plant leaf disease detection and diagnosis using Image Processing PROJECT BRIEF Identification of plant disease using image processing technic by a simply load the image into MATLAB and give the solution to disease. TOOL

KEY CHALLENGES &

LEARNINGS

MATLAB 7.4 version

Identification and Solve the bugs in code and add some more features to code.

Hardware connection

TITLE Router 1x3 – RTL design and Verification

PROJECT BRIEF The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2. TOOL

KEY CHALLENGES &

LEARNINGS

Questasim and ISE

Architected the block level structure for the design

Implemented RTL using Verilog HDL.

Architected the class based verification environment using systemVerilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

TITLE UART- IP Core – Verification

PROJECT BRIEF

TOOL

KEY CHALLENGES &

LEARNINGS

The UART IP core provides serial communication capabilities, which allow communication with modem or other external devices. UART will operate in three different modes – Simplex mode, Full Duplex mode and loopback mode

Riviera Pro - Aldec

Architected the class based verification environment in UVM

Defined Verification Plan

Verified the RTL module using SystemVerilog

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