Shubham Dewangan

E mail: ac80mv@r.postjobfree.com

Mobile: +91-798-***-****

LinkedIn ID: www.linkedin.com/in/shubhamdewangan/

Address: Gottigere, Bannerghatta Road, Bengaluru, Karnataka-560083

Summary of Qualifications

• Good understanding of the ASIC design flow

• Good Understanding on Digital Design concepts – Combinational and

Sequential circuits

• Extensive experience in writing RTL models using Verilog HDL

• Good experience in writing Test benches using SystemVerilog and UVM

• Very good knowledge in verification methodologies

• Experience in using industry standard EDA tools for the front-end design and verification

Educational Qualification:

Bachelor of Engineering,

Shri Shankaracharya Institute of Engineering and Technology, Bhilai

Dicipline: Electronics and Telecommunication Engineering

Percentage: 70.23%

Year: 2017

Higher Secondary School,

Priyadarshni Jr. College, Visakhapatnam

Dicipline: APBSE

Percentage: 65.2%

Year: 2013

High School,

St. Xavier’s High School, Jagdalpur

Dicipline: ICSE

Percentage: 60%

Year: 2011

Professional Qualification:

Advanced VLSI Design and Verification course

Maven Silicon VLSI Design and Training Center, Bengaluru.

JULY-2018 to JAN-2019.

VLSI Domain Skills:

• HDL : Verilog

• HVL : SystemVerilog

• Verification Methodology : Coverage Driven Verification

• TB Methodology : UVM

• Protocols : SPI

• EDA Tools : Riviera Pro – Aldec, ISE – Xilinx

• Domain : ASIC/FPGA front-end Design and Verification

• Knowledge : RTL Coding, FSM based design, Code Coverage, Functional Coverage, Assertions for RTL

VLSI Project:

SPI Controller Core - Verification

HVL : SystemVerilog

TB Methodology : UVM

EDA Tools : Riviera Pro – Aldec

Description: The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves.

Responsibilities:

• Architected the class based verification environment in UVM

• Defined Verification Plan

• Verified the RTL module using SystemVerilog

• Generated functional and code coverage for the RTL verification sign-off.

Academic Project:

Security System using OTP in “EMBEDDED SYSTEM”

• Project concludes that OTP (One Time Password) can be used in the field of security purpose.

• We have designed a system to give complete security to the sensitive data by generating OTP over a certain time limit delay allotted in the program.

• We are using GSM module to receive OTP and verify authentic user login. The design principle of system is trying to eliminate the negative influence of human factors as much as possible.

• Secure than the original login system sign-off.

Curriculum Project:

Router 1x3 – RTL design and Verification

Description:

• The router accepts data packets on a single 8-bit port and routes them to one of the three output channels: channel0, channel1 or channel2.

• Architected the block level structure for the design and described the functionality using Verilog HDL.

• Verified Router1x3 using UVM Methodology.

• Generated functional and code coverage for the RTL Verification.

• Synthesized the design sign-off.

References:

• On Request

Declaration:

I hereby declare that the above provided information is correct to the best of my knowledge.

Place : Bengaluru

Date : 6th April, 2019

SHUBHAM DEWANGAN

Contact this candidate