Design Engineering

UPPALAPATI JAGADEESH Hennur main road, Geddalahalli, Email: ************@*****.***

BDS Garden, 10th cross #1/1, Mobile: +91-886*******

Kothnur Post, Bengaluru-560077 LinkedIn ID ************@*****.***

Summary of Qualifications

Good understanding of the ASIC and FPGA design flow

Extensive experience in writing RTL models using Verilog HDL.

Good experience in writing Test benches using SystemVerilog and UVM

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and verification

VLSI Domain Skills

HDL : Verilog

HVL : SystemVerilog

Verification Methodology : Coverage Driven Verification, Assertion Based Verification

TB Methodology : UVM

EDA Tools : Riviera Pro – Aldec

ISE – Xilinx

Domain : ASIC/FPGA front-end Design and Verification

Knowledge : RTL Coding, FSM based design,

Simulation, Code Coverage,

Functional Coverage, Synthesis,

Static Timing Analysis, ABV- SVA

Professional Qualification

Advanced VLSI Design and Verification course

Maven Silicon VLSI Design and Training Center, Bangalore

Oct 2018 to Apr 2019

Educational Qualification

Bachelor of Engineering, Sai Vidya Institute of Technology, Bengaluru Visvesvaraya Technological University, Karnataka, India Discipline: Electronics & Communication Engineering Percentage: 55% second Class

Year: May 2018

Achievements/Publications

Presented a paper on “Wireless communication and Networking” at National conference reference NCWCN – 2018.

VLSI Projects

AHB2APB Bridge IP Core Verification

HVL: System Verilog

TB Methodology: UVM

EDA Tool: Riviera Pro – Aldec

Description: The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses.

Responsibilities:

Architected the class based verification environment in UVM.

Defined Verification Plan

Verified the RTL module with UVM Test Bench with different test scenarios like single READ, WRITE & Burst READ, WRITE with different burst lengths.

Generated functional and code coverage for the RTL verification sign-off.

SPI Controller Core - Verification

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Riviera Pro - Aldec

Description: The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves.

Responsibilities:

Architected the class based verification environment in UVM

Defined Verification Plan

Verified the RTL module using SystemVerilog

Generated functional and code coverage for the RTL verification sign-off

Curriculum Project

Router 1x3 – RTL design and Verification

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: ISE

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

Responsibilities:

Architected the block level structure for the design

Implemented RTL using Verilog HDL.

Architected the class based verification environment using SystemVerilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design.

Engineering Project

Multi-purpose surveillance rover for detecting hospitable environment

In this project rover can be implemented to provide safety to the mine workers

The sensors are implemented in the rover to detect the methane gas in the mining areas.

The rover monitoring system is capable of sending the message to the handset regarding the gas detection automatically.

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