| Resume alert | Resumes 51 - 60 of 412 |
Engineering C
Bangalore, Karnataka, India
... Training on embedded system using AVR microcontroller Key Learning’s- Digital system Designing Hardware Interfacing of FPGA and CPLD Hobbies/Interest Reading books especially of General knowledge/ teaching Place:-Bhopal Arjun yadav Date :- - 2019 Oct 13
... Training on embedded system using AVR microcontroller Key Learning’s- Digital system Designing Hardware Interfacing of FPGA and CPLD Hobbies/Interest Reading books especially of General knowledge/ teaching Place:-Bhopal Arjun yadav Date :- - 2019 Oct 13
Developer Software
Bangalore, Karnataka, India
... Page 2 Academic Project-BE(ECE) TITLE: VITERBI DECODER DESIGN FOR SOFTWARE DEFINED RADIO ON FPGA (VLSI DOMAIN) DESCRIPTION: A) Software defined radio adapts various modulation schemes, encoding techniques by changing its configuration. SDR reduces ... - 2019 Sep 25
... Page 2 Academic Project-BE(ECE) TITLE: VITERBI DECODER DESIGN FOR SOFTWARE DEFINED RADIO ON FPGA (VLSI DOMAIN) DESCRIPTION: A) Software defined radio adapts various modulation schemes, encoding techniques by changing its configuration. SDR reduces ... - 2019 Sep 25
Design Electrical
Gottigere, Karnataka, India
... UVM Protocols : AXI, AHB, UART, I2C, SPI EDA Tools : QuestaSim – Mentor Graphics, Riviera Pro – Aldec, ISE – Xilinx Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional ... - 2019 Sep 11
... UVM Protocols : AXI, AHB, UART, I2C, SPI EDA Tools : QuestaSim – Mentor Graphics, Riviera Pro – Aldec, ISE – Xilinx Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional ... - 2019 Sep 11
Electronics graduate,pursuing Design for testing,verilog,digital elect
HSR Layout, Karnataka, India
... 2’s complement of a number which does the work faster than conventional method and the classical adder structure has been replaced by Ling adder for reducing delay.Therefore a faster version of multiplication algorithm can be implemented on FPGA. ... - 2019 Sep 09
... 2’s complement of a number which does the work faster than conventional method and the classical adder structure has been replaced by Ling adder for reducing delay.Therefore a faster version of multiplication algorithm can be implemented on FPGA. ... - 2019 Sep 09
Engineer Engineering
Vasant Nagar, Karnataka, India
... PROJECT UNDERTAKEN IN M.TECH : “Design and Implementation of FPGA based closed loop V/f speed control of Induction Motor Employed for Industrial Applications” Team size: 1 SEMINARS ATTENDED: PROJECT UNDERTAKEN IN B.E: “GSM Based Vehicle Battery ... - 2019 Sep 08
... PROJECT UNDERTAKEN IN M.TECH : “Design and Implementation of FPGA based closed loop V/f speed control of Induction Motor Employed for Industrial Applications” Team size: 1 SEMINARS ATTENDED: PROJECT UNDERTAKEN IN B.E: “GSM Based Vehicle Battery ... - 2019 Sep 08
Project Security
Vasant Nagar, Karnataka, India
... TeleCommunication Networking TECHNICALEXPERTISE CoreSkills:VLSIdesign Platform:Linux(redhatenterpriselinux5) Software:Cadancetool,Incisive_Enterprise_Simulator,NCSIMverilogSimulator Platform:Windows732bit Software:Xilinx12.1,FPGA:Spartan6XC6SLX45. ... - 2019 Aug 27
... TeleCommunication Networking TECHNICALEXPERTISE CoreSkills:VLSIdesign Platform:Linux(redhatenterpriselinux5) Software:Cadancetool,Incisive_Enterprise_Simulator,NCSIMverilogSimulator Platform:Windows732bit Software:Xilinx12.1,FPGA:Spartan6XC6SLX45. ... - 2019 Aug 27
Hardware Engineer
Vasant Nagar, Karnataka, India
... Cadence Virtuoso, Cadence Encounter RTL Compiler • Simulation Tool: PSpice (Spectre), OrCAD Schematic Capture, TINA Spice • FPGA Synthesis: Xilinx ISE, Vivado • Scripting: Python, Linux/Unix shell scripting, Tcl/Tk scripting • Programming Languages: ... - 2019 Aug 20
... Cadence Virtuoso, Cadence Encounter RTL Compiler • Simulation Tool: PSpice (Spectre), OrCAD Schematic Capture, TINA Spice • FPGA Synthesis: Xilinx ISE, Vivado • Scripting: Python, Linux/Unix shell scripting, Tcl/Tk scripting • Programming Languages: ... - 2019 Aug 20
Software Developer Assistant
Vasant Nagar, Karnataka, India
... 2)Project name: Snake game using FPGA board Software : Xilinx vivado using verilog HDL. Team Size : 3 members Role : Front end designer. Organization : GVIT Project Supervisor (s): Mr.Aravind Kumar (Assistant Professor Dept. of ECE) Area/Domain of ... - 2019 Aug 17
... 2)Project name: Snake game using FPGA board Software : Xilinx vivado using verilog HDL. Team Size : 3 members Role : Front end designer. Organization : GVIT Project Supervisor (s): Mr.Aravind Kumar (Assistant Professor Dept. of ECE) Area/Domain of ... - 2019 Aug 17
Design Power
Vasant Nagar, Karnataka, India
... PERL(beginner level), System Verilog(beginner level) EDA TOOLS Synopsys EDA tools: IC compiler Prime time Cadence EDA tool: Cadence virtuoso Mentor graphics: Modelsim(HDL simulation) FPGA Synthesis Tool: Quartus altera Xilinx Vivado Design Suite. ... - 2019 Aug 08
... PERL(beginner level), System Verilog(beginner level) EDA TOOLS Synopsys EDA tools: IC compiler Prime time Cadence EDA tool: Cadence virtuoso Mentor graphics: Modelsim(HDL simulation) FPGA Synthesis Tool: Quartus altera Xilinx Vivado Design Suite. ... - 2019 Aug 08
Design Project
Koramangala, Karnataka, India
... Hardware Systems : NXP ARM Cortex M3 (for Embedded Applications), Basys3 FPGA Board (Processor Based System Design) Technical Skills : Physical Design, Analog & Mixed Signal Circuit Design, STA and PCB Design. Hands on Analysis of different types of ... - 2019 Aug 07
... Hardware Systems : NXP ARM Cortex M3 (for Embedded Applications), Basys3 FPGA Board (Processor Based System Design) Technical Skills : Physical Design, Analog & Mixed Signal Circuit Design, STA and PCB Design. Hands on Analysis of different types of ... - 2019 Aug 07