Verilog, System Verilog, UVM, SOC Verification, ASIC Verification

Mobile: +91-868*******

Email Id: *******@*****.***

LinkedIn:https://www.linkedin.com/i

n/praveen-naddi-399a4ba3/

Address: D.NO: 1-104,

Putrela (P&V),

Vissannapeta(MD)

Krishna (DT),

Andhra Pradesh,

PIN: 521227.

The following are the best skills

which I believe are applicable to the

position I have applied for

HDL : Verilog

HVL : System Verilog

Protocols : AMBA, AHB,

APB, SPI,

AHB-APB

Simulators : Riviera Pro,

Questasim,

Modelsim

Verification

Methodologies : UVM

Learn new technologies

Watching movies

Playing Cricket

Possesses great analytical and

problem-solving skills

Logical & Structured thinking

Ability to work in any technology

CAREER INTEREST:

Seeking a Design Verification Engineer position that enables me to utilize my skills within the field to make a positive contribution to the company.

EXPERIENCE:

Having 1year of experience in SkandySys as a Design Verification Engineer.

March 2018 – March 2019

Location – Bangalore

Worked as an Intern for 1 year at GIET College, Rajahmundry for Verilog, Xilinx.

September 2016 – December 2017

Done VLSI Design and Verification course at Maven silicon, Bangalore.

June 2017 – January 2018

Expertise Skills:

• Experienced in writing Test benches in System Verilog / UVM.

• Developed a test plan and setup the test bench and the environment.

• Debugged RTL using simulators like NC-Verilog,

Simvision, and Synopsys VCS.

• Involved in writing and modifying Perl scripts.

• Got an opportunity to work with EDA tools like Questa- sim, Modelsim, and Rivera-Pro.

EDUCATION:

M. TECH - DECS, 80%, May 2017, GIET College of Engineering, AP.

B. TECH - ECE, 63%, May 2014, Sri Saradhi College of Engineerin AP.

Intermediate 70%, May 2010 Chaitanya Junior College, AP.

ICSE, 66%, March 2008, SDA High School, AP.

PRAVEEN KUMAR NADDI

Aspiring Design Verification Engineer

CONTACT

TECHNICAL SKILLS

21

st

CENTURY FLUENCIES

OTHER INTERESTS

Projects

Project 1 : Minimal Open RISC SOC (Skandysys)

Platform : Linux

Language

Verification

Methodology

: System Verilog

: UVM

Tools : Questa-sim

Features

Objective

My role

• OR 1200 implementation.

• Resizable on-chip memory.

• JTAG debug featuring a multitude of cables.

• Start-up option to automatically load your firmware on start-up from an external SPI memory.

• UART and Ethernet modules.

• FPGA generic and specific code (Xilinx & Altera) for memory, clock adaption and JTAG tap.

• System configuration in a single definition file.

• Example firmware’s using UART and Ethernet.

• Test bench included, simulating target software and system.

• The main objective of this project is to synthesizable SOC which can be uploaded to every FPGA compatible boards without changing its code.

• In order to deliver this kind of project we need a standard memory implementation and Advance Debug System.

• Prepared the test bench architecture.

• Integrated the SOC with peripherals and created TB top and instantiated the all modules and released clock, reset and backloaded the RAM with some data by readmem.h command.

• Implemented Wishbone slave BFM.

• Created the test environment in System Verilog.

Project 2 : SPI – Master Core – Verification (Skandysys) Platform : Linux

Language

Verification

Methodology

: System Verilog

: UVM

EDA Tools

Objective

: Riviera Pro and ISE

• Serial peripheral interfaces are providing economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other.

My Role

• Architected the class-based verification environment in UVM.

• Random stimulus generation.

• Implemented Test cases.

• Verified the RTL module using System Verilog.

Project 3 : Generic AHB Agent (Skandysys)

Platform

Language

: Linux

: System Verilog

Verification

Methodology

EDA Tools

: UVM

: Xilinx ISE and Aldec Riviera-PRO.

Features

• Configurable number of master or slave agents

• Configurable as active or passive agent

• Supports both Burst transfer and Split transactions.

• The environment, creates agents, virtual sequencer, setting the environment config to components

• Test, we will get the environment config and update the agents config information and set it back

• Top module, we will create environment config and agent config and set virtual interface to the corresponding agent and set the environment config

My Role

Project 4

Platform

Language

Verification

Methodology

EDA Tools

Objective

My Role

REFERENCES

DECLARATION

• Writing a Driver logic for AHB

• Writing sequences

• Running different test cases

: Router 1X3 – RTL Design and Verification (Maven silicon)

: Linux

: System Verilog

: UVM

: Xilinx ISE and Aldec Riviera-PRO.

• The Router accepts data packets on a single 8-bit port routes them to one of the three Output channels Channel, Channel0, Channel1,Channel2

• Architected the design.

• Implemented RTL using Verilog HDL

• Architected the class based verification environment using system Verilog

• Verified the RTL model using System Verilog

• Generated functional and code coverage for the RTL verification sign-off

: References will be provided on request.

: The Information given above is true to the best of my knowledge. SIGNATURE

PRAVEEN KUMAR NADDI

Contact this candidate