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Design Engineering

Location:
Vasant Nagar, Karnataka, India
Posted:
July 12, 2019

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Resume:

OGIRALA MANI BHARGAV

Gottigere, Near Meenakshi layout, Email: ac9s7g@r.postjobfree.com

Bangalore, Pincode-560083 Mobile: +91-954*******

LinkedIn ID: https://www.linkedin.com/in/manibhargav-ogirala-23a518172/ Summary of Qualifications

Good understanding of the ASIC and FPGA design flow

Extensive experience in writing RTL models using Verilog HDL.

Good experience in writing Test benches using SystemVerilog and UVM

Very good knowledge in verification methodologies

Experience in using industry standard EDA tools for the front-end design and verification VLSI Domain Skills

HDL : Verilog

HVL : SystemVerilog

Verification Methodology : Coverage Driven Verification, Assertion Based Verification TB Methodology : UVM

Protocols : SPI

EDA Tools : Riviera Pro – Aldec

ISE – Xilinx

Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design,

Simulation, Code Coverage,

Functional Coverage, Synthesis,

Static Timing Analysis, ABV- SVA

Professional Qualification

Advanced VLSI Design and Verification course from Maven Silicon VLSI Design and Training Center, Bangalore

Educational Qualification

Completed Bachelor of Technology in the stream of Electronics and Communication Engineering from NRI Institute of Technology in 2018 affiliated by JNTU Kakinada With 63%.

Passed from Narayana Junior College in 2014 with 85%

Passed from Ravindra Bharathi Public School in 2012 with 8.3 GPA VLSI Projects

AHB2APB Bridge IP Core Design

HDL: Verilog

EDA Tool : ISE-Xlinx

Description:The AHB to APB bridge is designed as an AHB slave converts AHB transactions to APB transactions by implementing pipelining at AHB slave interface. Thus, the bridge supports AHB burst transfers.

Responsibilities:

Architected the block level structure for the bridge.

Develop the Verilog RTL for each block.

Verified each block with different transfers like single READ,WRITE & Burst READ,WRITE.

Synthesized the design.

Generate code coverage report for RTL Design signoff. SPI Controller Core – Verification

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Riviera Pro – Aldec

Description: The SPI IP core provides serial communication capabilities with external device of variable length of transfer word. This core can be configured to connect with 32 slaves. Responsibilities:

Architected the class based verification environment in UVM

Defined Verification Plan

Verified the RTL module using SystemVerilog

Generated functional and code coverage for the RTL verification sign-off Project

Curriculum Project

Router 1x3 – RTL Design and Verification

HDL: Verilog

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Questasim and ISE

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2. Responsibilities:

Implemented RTL using Verilog HDL.

Architected the class based verification environment using SystemVerilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design.

Engineering Project

Project Name: Walking Stick with Heartattack Detection Tool : ARDUINO UNO

References

On Request

Place: Bangalore OGIRALA MANI BHARGAV



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