To pursue a challenging career and be a part of progressive organization that gives a scope to enhance my knowledge and utilizing my skills towards the growth of the organization. SUMMARY OF QUALIFICATIONS:
Good understanding of the ASIC and FPGA design flow
Extensive experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog and UVM
Very good knowledge in verification methodologies
Experience in using industry standard EDA tools for the front-end design and verification TECHNICAL SKILLS:
Programming languages : Basic Knowledge in C, Verilog HDL.
Design Tools : TASM, CADENCE (180nm) technology. VLSI Domain Skills
HDL : Verilog
HVL : SystemVerilog
Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA
TB Methodology : UVM
Protocols : AXI, AHB, UART, I2C, SPI
EDA Tool : Questasim and ISE
Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis,
Static Timing Analysis, ABV- SVA
Maven Silicon Certified Advanced VLSI Design and Verification course from Maven Silicon VLSI Design and Training Center, Bangalore Master of Technology, G.Pulla Reddy Engineering College, Kurnool University: JNTU Anantapur, Andhra pradesh, India
Specialization: VLSI & Embedded Systems
Discipline: Electronics &Communication Engineering Percentage: 7.35(CGPA)First Class
Year of Passed Out: 2018
Bachelor of Technology, G.Pullaiah College of Engineering and Technology, Kurnool University: JNTU Anantapur, Andhra pradesh, India
Discipline: Electronics & Communication Engineering Percentage: 70% First Class with Distinction
Year of Passed Out: 2016
Project Intern, Maven Silicon Six months experience in front end design and verification VLSI PROJECTS
 Router 1x3 – RTL design and Verification
TB Methodology: UVM
EDA Tools: Questasim and ISE
Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2. Responsibilities:
Architected the design and Implemented RTL using Verilog HDL
Architected the class based verification environment using system Verilog
Verified the RTL model using SystemVerilog
Generated functional and code coverage for the RTL verification sign-off
Synthesized the design
 AHB2APB Bridge IP Core Verification
HVL: System Verilog
TB Methodology: UVM
EDA Tool: Questasim
Description: The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses Responsibilities:
Architected the class based verification environment in UVM
Verified the RTL module with single master and single slave
Generated functional and code coverage for the RTL verification sign-off ENGINEERING PROJECT:
Main Project (M. Tech):
Topic: A Low-Energy and High-Performance Voltage Level Shifter Using Dual-Supply Applications Description:
Main theme of this project is to design a low-energy and high-performance voltage level- shifting circuit is to capable of shifting low core voltage to high input-output voltage. The circuit performance is due to the fact not only strengthen the pull-up device and slowly reduced when the pull- down device is pulling output node to down, but the strength of the pull-down device is also increases low-power circuit.
Main Project (B. Tech):
Topic: A Rescue System of an Advanced Ambulance Using Prioritized Traffic Switching Description:
The main theme behind this scheme is to provide a smooth flow for the ambulance to reach the hospitals in time. The ambulance is controlled by the central unit which gives the shortest route to the ambulance and also controls the traffic light according to the ambulance location and thus reaching the hospital safely. The server also determines the location of the accident spot through the sensor systems in the vehicle which encountered the accident and thus the server walks through the ambulance to the spot. This scheme is fully automated, thus it finds the accident spot, controls the traffic lights, helping to reach the hospital in time.
Attended workshop on Embedded Systems conducted in G.Pullaiah College of Engineering and Technology.
Attended workshop on Robotics conducted in G.Pulla Reddy Engineering College. INTERNSHIP:
Six months Internship in “Aquila Technologies” as a part of Diploma course. STRENGTHS:
Able to work independently and make good team work.
Passion to learn new technologies.
Highly dedicated and self-motivated.
Pre-Planning, willing to take up challenges.
Flexible to work anywhere.
Father’s Name : D.Shaik shavali
Date of Birth : 10-06-1995
Gender : Male
Marital status : Single
Permanent Address : H.No.7-96/1, Narnoor (v), Orvakal (m), Kurnool (Dist) Languages known : Telugu, English & Hindi
Hobbies : Listening Music, Browsing & Cooking
I hereby declare that the information furnished above is true to the best of my knowledge. Place: