RAMAYANAMTHARUNKUMAR

MailId:tharun******@ac8ofy@r.postjobfree.com

Mobileno:+91-773*******

B.Tech(ECE)

SkillSet

HDLs Hardware Scripting Programming Tools

Language

Verilog, ZedBoard, TCL(basic) C(basic) QuestaSim,

FPGA,SV Xilinx7series Vivado

FPGA

MajorProjects

DesignandFPGAimplementationofHighspeedfloatingmultiplierusingDaddaalgorithm Theaimofthisprojectistodevelopa32-bithighspeedfloatingpointmultiplierusingDADDAalgorithm.The designusedpurecombinationalcircuitsthatarefulladders,halfaddersandlogicgates.Thecodewaswritten inVerilogandsimulatedwithsuitabletestvectorslikeintegersandfloatingpointnumbersusingQuestaSim. Thismultiplieristhebestoptimalmultiplier.Thedesignhasbeensynthesizedandcheckedfortimingusing VivadoandimplementedonZedBoard.Thedesignutilized92LUTs.Consumedpowerof7.34wanditis operatesatafrequencyof83.33MHz.

DesignandFPGAimplementationofBlockRAMmemorymodellingconfigurationscomparewithIP instantiation

TheaimofthisprojectistocomparetheBRAMmemoryconfigurationswiththeVerilogcodesintheIPcatalog. ThemajorblocksoftheprojectareincludessingleportRAM,simpledualportRAMandtruedualportRAM.The blocksaremodelledusingVerilogandfunctionalityischeckedbyusingQuestaSim.Thedesignhasbeen synthesizedandcheckedfortimingusingVivadotool.Theimplementedmodulesarecomparedwiththe programsalreadyavailableintheIPcatalogbyinstantiatingthedeviceutilizationofarea,powerandoperating frequencyparametersinthebothcases(inferringandinstantiation)weretabulated. DesignandFPGAImplementationofSerialPeripheralInterface(SPI)communicationprotocol Theaimofthisprojectistodevelopthecommunicationseriallybytebybytebetweenasinglemasterand multipleslaves.Thefullduplexcommunicationachievedbythisprotocol.Themainblocksofthisprotocolare SerialPeripheralStatusRegisters(SPSR),SerialPeripheralControlRegisters(SPCR)andSerialPeripheralData Registers(SPDR).Eachblockhasseparateflagstoindicatethecommunicationprocessingoftheprotocol. AchievedthedatafromthemastertoslaveandslavetomastersuccessfullybyusingMOSIandMISOpinsat thesameclockcycle.TheslaveselectionisdonebyusingSS(SlaveSelect)pinwhichisinactivelow. MinorProjects

DesignandFPGAimplementationofVGAController

TheaimofthisprojectistodevelopaVGAcontrollerwhichisusedtodisplaythecolourspectrumonthe monitor.ThemajorblocksoftheVGAcontrollerincludeaclockdivider,Horizontalsyncgenerator,Verticalsync generatorandRGBgenerator.TheblocksaremodelledusingVerilogandfunctionalityischeckedusing QuestaSim.ThedesignhasbeensynthesizedandcheckedfortimingusingVivadoandimplementedonZed Board.Thedeviceutilizationwas40LUTsand24FFs.Thepowerutilizedis3.130wandoperatesatafrequency of89.43MHz.

Implementationofinterprocesscommunicationbetweencentralprocessingunitandmemoryunit Themainaimofthisprojectistobuilttheinterprocesscommunicationbetweencentralprocessingunitand memoryunitbyusinginterfacesignals.Implementedaninterfaceprogramtosharethedatabetweenthe centralprocessingunitandmemoryunit.ThiscodewasdevelopedinQuestaSimsoftwaretool.Allpossibletest casesareprovided.Thecodecoverageandfunctionalcoverageareachieved100%. EducationalQualifications

Course AggregatePercentage University Institution

B.Tech(ECE) JawaharlalNehru MadanapalleInstituteof 2015-2018 73% TechnologyUniversity TechnologyandScience, A.P.

Diploma LoyolaPolytechniccollege,

2012-2015 78% SBTET Pulivendula

SSC

2012 87% SSC Z.P.HighSchool,A.P.

AdditionalInformation

Awards&Achievements

1.Won1

st

prizeincollegeseminarcompetition.

2.Participatedinmandallevelessaywritingcompetition. Declaration

Idoherebyconfirmthattheinformationgivenaboveistrueandtothebestofmyknowledge. Signature

RamayanamTharunkumar

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