| Resume alert | Resumes 61 - 70 of 197 |
Design Electrical Engineering
Los Angeles, CA
... Osmania University, India, B.E in Electronics and Communications Engineering (CGPA: - 3.86/4.0) Graduated: May 2015 TECHNICAL SKILLS • Languages : System Verilog, Verilog, C, C++, Python • Tools : QuestaSim, Quartus II, Matlab, Cadence Virtuoso, ... - 2017 Sep 18
... Osmania University, India, B.E in Electronics and Communications Engineering (CGPA: - 3.86/4.0) Graduated: May 2015 TECHNICAL SKILLS • Languages : System Verilog, Verilog, C, C++, Python • Tools : QuestaSim, Quartus II, Matlab, Cadence Virtuoso, ... - 2017 Sep 18
Verilog, VHDL, Python, C, C#, PL/SQL
Los Angeles, CA
... TECHNICAL SKILLS Programming Languages: Verilog, VHDL, Python, C, C#, PL/SQL Applications and Tools: ModelSim, Cadence Virtuoso, Xilinx ISE, Prime Time, Design Compiler, Conformal, Synopsys, Cadence First Encounter, .Net, Lab Windows, Kiel ACADEMIC ... - 2017 Sep 15
... TECHNICAL SKILLS Programming Languages: Verilog, VHDL, Python, C, C#, PL/SQL Applications and Tools: ModelSim, Cadence Virtuoso, Xilinx ISE, Prime Time, Design Compiler, Conformal, Synopsys, Cadence First Encounter, .Net, Lab Windows, Kiel ACADEMIC ... - 2017 Sep 15
Engineering Computer
Walnut, CA
... / Financial Analysis Computer C / Java / JavaScript / Python / SQL Linux / Shell Script Assembly / MIPS / VHDL PSpice / OrCAD / Cadence Mathematica / MATLAB / MS Office Electrical Analog Circuit - design and analysis of BJT and MOSFET differential ... - 2017 Sep 08
... / Financial Analysis Computer C / Java / JavaScript / Python / SQL Linux / Shell Script Assembly / MIPS / VHDL PSpice / OrCAD / Cadence Mathematica / MATLAB / MS Office Electrical Analog Circuit - design and analysis of BJT and MOSFET differential ... - 2017 Sep 08
Design Electrical Engineering
Los Angeles, CA
... 1KB SRAM Design in Cadence Virtuoso. Jun’16 Designed the schematic and layout of a 1024 bit SRAM in 200nm technology. The SRAM design consists of Row Decoder, Column Multiplexer, Pre Charging Circuitry, Sense Amplifiers and Output Registers. ... - 2017 Aug 17
... 1KB SRAM Design in Cadence Virtuoso. Jun’16 Designed the schematic and layout of a 1024 bit SRAM in 200nm technology. The SRAM design consists of Row Decoder, Column Multiplexer, Pre Charging Circuitry, Sense Amplifiers and Output Registers. ... - 2017 Aug 17
ASIC design verification engineer
Los Angeles, CA
Vignesh Saravanan ac1q5u@r.postjobfree.com SOFTWARE SKILLS EDA TOOLS – Cadence Encounter RTL compiler ultra Cadence Virtuoso Mentor graphics IC station Mentor graphics Calibre Leonardo Spectrum Model sim Synopsys primetime Altera Quartus II Xilinx ... - 2017 Aug 10
Vignesh Saravanan ac1q5u@r.postjobfree.com SOFTWARE SKILLS EDA TOOLS – Cadence Encounter RTL compiler ultra Cadence Virtuoso Mentor graphics IC station Mentor graphics Calibre Leonardo Spectrum Model sim Synopsys primetime Altera Quartus II Xilinx ... - 2017 Aug 10
Engineering Design
Fullerton, CA
... analyzer drive TECHNICAL SKILLS Programing Tools Lab OS Protocol: Development and Equipment’s: and Applications: IDE: languages: Platform: C, Cadence Windows, LTE, Oscilloscope, FPGA, C++SPI,, Arduino, VHDL, RS232, Virtuoso, Unix/Spectrum Verilog, ... - 2017 Aug 04
... analyzer drive TECHNICAL SKILLS Programing Tools Lab OS Protocol: Development and Equipment’s: and Applications: IDE: languages: Platform: C, Cadence Windows, LTE, Oscilloscope, FPGA, C++SPI,, Arduino, VHDL, RS232, Virtuoso, Unix/Spectrum Verilog, ... - 2017 Aug 04
Customer Service Management
Arcadia, CA, 91006
... Assisted the Cadre team in the implementation of a new WMS (Cadence) as well as the project manager for a new LMS (TZA) for the company. Coordination of labor resources for receiving and inventory control functions, performance of various duties ... - 2017 Apr 27
... Assisted the Cadre team in the implementation of a new WMS (Cadence) as well as the project manager for a new LMS (TZA) for the company. Coordination of labor resources for receiving and inventory control functions, performance of various duties ... - 2017 Apr 27
Design Engineer State University
Los Angeles, CA
... Cadence: Allegro, Orcad Matlab/Simulink Research Corporation of the University of Hawai’i Jan 2015 –Present(Contractor) Recommend troubleshooting strategies and tests to operate a new 7 antenna correlator for the Yuan T Lee Array on Mauna Loa, Hi. ... - 2017 Apr 05
... Cadence: Allegro, Orcad Matlab/Simulink Research Corporation of the University of Hawai’i Jan 2015 –Present(Contractor) Recommend troubleshooting strategies and tests to operate a new 7 antenna correlator for the Yuan T Lee Array on Mauna Loa, Hi. ... - 2017 Apr 05
Engineer Design
Fullerton, CA
... ChipScope Pro Tools Altera Quartus Actel/Microsemi Libero Software ModelSim Actel Design Software Aldec Active-HDL Synopsys Cadence BuildGates Cadence NC-VHDL Orcad DxDesigner EXPERIENCE SENIOR ENGINEER (May 2016 - present) Jet Propulsion Laboratory ... - 2017 Mar 28
... ChipScope Pro Tools Altera Quartus Actel/Microsemi Libero Software ModelSim Actel Design Software Aldec Active-HDL Synopsys Cadence BuildGates Cadence NC-VHDL Orcad DxDesigner EXPERIENCE SENIOR ENGINEER (May 2016 - present) Jet Propulsion Laboratory ... - 2017 Mar 28
FPGA / ASIC Design Engineer
Fullerton, CA
... CADENCE DESIGN SYSTEMS 3030 Old Ranch Parkway, Suite 210/300, Seal Beach, CA (4/00-9/03) Field Solutions Create Division (Formerly JTA Research Inc.) ASIC Design Engineer / Digital Logic Design Engineer My primary responsibilities included the ... - 2017 Mar 25
... CADENCE DESIGN SYSTEMS 3030 Old Ranch Parkway, Suite 210/300, Seal Beach, CA (4/00-9/03) Field Solutions Create Division (Formerly JTA Research Inc.) ASIC Design Engineer / Digital Logic Design Engineer My primary responsibilities included the ... - 2017 Mar 25