| Resume alert | Resumes 31 - 40 of 197 |
Electrical Engineer Design
Los Angeles, CA
... Used Cadence design tools for functional, logic and physical design and verification. University of Pune, India Aug 2012 - May 2016 • Bachelor of Engineering (B.E.) in Electronics and Telecommunication, GPA 3.8 Majored in Embedded Systems with a ... - 2020 Aug 10
... Used Cadence design tools for functional, logic and physical design and verification. University of Pune, India Aug 2012 - May 2016 • Bachelor of Engineering (B.E.) in Electronics and Telecommunication, GPA 3.8 Majored in Embedded Systems with a ... - 2020 Aug 10
Electrical Engineer Power
Redondo Beach, CA
... analysis results for customers Maintaining constant communication with customers to answer technical questions SKILLS CAD Tools: Cadence OrCAD, LabVIEW, ETAP, PSpice, Spectre, LTSpice, MATLAB SPICE Modeling: Modeling Parts such as Tantulum/Ceramic ... - 2020 Jul 20
... analysis results for customers Maintaining constant communication with customers to answer technical questions SKILLS CAD Tools: Cadence OrCAD, LabVIEW, ETAP, PSpice, Spectre, LTSpice, MATLAB SPICE Modeling: Modeling Parts such as Tantulum/Ceramic ... - 2020 Jul 20
Design Engineer Engineering
Los Angeles, CA
... EDA Tools : UVM Framework, ModelSim, Xilinx Vivado Design Suite, Cadence Virtuoso, Synopsys VCS Hardware : ZedBoard Zynq-7000 ARM/FPGA SoC Development Board, Xilinx FPGA Virtex 6, Arduino Uno. Work Experience: Belkin International. CA, USA Design ... - 2020 Jul 13
... EDA Tools : UVM Framework, ModelSim, Xilinx Vivado Design Suite, Cadence Virtuoso, Synopsys VCS Hardware : ZedBoard Zynq-7000 ARM/FPGA SoC Development Board, Xilinx FPGA Virtex 6, Arduino Uno. Work Experience: Belkin International. CA, USA Design ... - 2020 Jul 13
Medical Devices/ Quality/ Development/ Validation/ R&D Engineering
Los Angeles, CA
... and Applications: MATLAB, LabVIEW, AutoCAD, Solidworks, P-Spice, Simulink, HFSS, CADENCE Data Analysis and Statistics: JMP, Minitab (DOE, Regression Analysis, ANOVA, Factorial Design) Project Management and End-to-End Product Lifecycle Development. ... - 2020 Jul 03
... and Applications: MATLAB, LabVIEW, AutoCAD, Solidworks, P-Spice, Simulink, HFSS, CADENCE Data Analysis and Statistics: JMP, Minitab (DOE, Regression Analysis, ANOVA, Factorial Design) Project Management and End-to-End Product Lifecycle Development. ... - 2020 Jul 03
Marketing Digital
El Segundo, CA
... multiple animation projects for broadcast & digital distribution • Led complete reevaluation and prioritization of digital marketing initiatives with a focus on story-telling, cadence and proper demographic targeting for each platform (e.g. ... - 2020 Jun 29
... multiple animation projects for broadcast & digital distribution • Led complete reevaluation and prioritization of digital marketing initiatives with a focus on story-telling, cadence and proper demographic targeting for each platform (e.g. ... - 2020 Jun 29
Manager Scrum
Santa Monica, CA
... Assessed and organize the delivery processes and cadence for teams to effectively deliver against our objectives. Acted as servant leader and Scrum Master. Evangelized engineering excellence and drive Agile and other best practices. Tracked metrics ... - 2020 Jun 16
... Assessed and organize the delivery processes and cadence for teams to effectively deliver against our objectives. Acted as servant leader and Scrum Master. Evangelized engineering excellence and drive Agile and other best practices. Tracked metrics ... - 2020 Jun 16
Electrical Engineer Design
Fullerton, CA
... AND EXPERTISE Interpersonal Skills: Creativity, Teamwork, Leadership, Positive Attitude, Empathy, Detail-oriented Tools: Cadence Virtuoso, Cadence Orcad, Eagle, Microwind, LT Spice, Proteus Proficient in: CMOS Technology, Analog Filter Design, IC ... - 2020 Jan 30
... AND EXPERTISE Interpersonal Skills: Creativity, Teamwork, Leadership, Positive Attitude, Empathy, Detail-oriented Tools: Cadence Virtuoso, Cadence Orcad, Eagle, Microwind, LT Spice, Proteus Proficient in: CMOS Technology, Analog Filter Design, IC ... - 2020 Jan 30
Electronic Engineer Design
Los Angeles, CA
... I have used Cadence FPGA to design and manufacture an ALU (Arithmetic and Logic Unit) microchip in three phases:- 1. Start with Verilog coding of the chip and then the logic flow at the circuit level using P-SPICE. 2. Then that Analog part which is ... - 2019 Nov 30
... I have used Cadence FPGA to design and manufacture an ALU (Arithmetic and Logic Unit) microchip in three phases:- 1. Start with Verilog coding of the chip and then the logic flow at the circuit level using P-SPICE. 2. Then that Analog part which is ... - 2019 Nov 30
Design Manager
Azusa, CA
... Altium Designer 19, AutoCAD Release 14 and 2000,Cadence Allegro 17.2, PCB Librarian XL, Orcad PCB Designer Professional, Capture Cis, Solidworks 2019, Draftsite 2019, User of Windows XP, 7, 10. Microsoft Office 2003. Experience Lead PCB Designer ... - 2019 Apr 29
... Altium Designer 19, AutoCAD Release 14 and 2000,Cadence Allegro 17.2, PCB Librarian XL, Orcad PCB Designer Professional, Capture Cis, Solidworks 2019, Draftsite 2019, User of Windows XP, 7, 10. Microsoft Office 2003. Experience Lead PCB Designer ... - 2019 Apr 29
Software Engineer
Alhambra, CA
... Cadence Virtuoso • PSPICE • FreeRTOS • Git • OpenCV • Linux • Atmel Studio • SolidWorks HARDWARES RaspBerry Pi • I2C • Oscilloscope/Function Generator • ARM-Cortex M4 SPOKEN &WRITTEN Native Proficiency: Spanish Limited Proficiency: Cantonese 1 - 2019 Apr 26
... Cadence Virtuoso • PSPICE • FreeRTOS • Git • OpenCV • Linux • Atmel Studio • SolidWorks HARDWARES RaspBerry Pi • I2C • Oscilloscope/Function Generator • ARM-Cortex M4 SPOKEN &WRITTEN Native Proficiency: Spanish Limited Proficiency: Cantonese 1 - 2019 Apr 26