| Resume alert | Resumes 51 - 60 of 680 |
Design Power
Bengaluru, KA, 560001, India
... Skills HDL: Verilog HVL: SystemVerilog Scripting Language: Perl Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology: UVM EDA Tool: Questasim and ISE, Modelsim Cadence Tool Suite (Virtuoso, ... - 2016 Nov 12
... Skills HDL: Verilog HVL: SystemVerilog Scripting Language: Perl Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology: UVM EDA Tool: Questasim and ISE, Modelsim Cadence Tool Suite (Virtuoso, ... - 2016 Nov 12
Design Test Cases
Bengaluru, KA, 560001, India
... TECHNICAL SKILLS HDL & HDVL : Verilog & System Verilog Verification Methodology : UVM. Scripting languages : Basics of Perl& Shell. Programming Languages : C EDA/Debug Tools : Xilinx ISE, VCS,Hspice,Libero,Rivera Pro. PROJECTS 1. Verification of ... - 2016 Nov 11
... TECHNICAL SKILLS HDL & HDVL : Verilog & System Verilog Verification Methodology : UVM. Scripting languages : Basics of Perl& Shell. Programming Languages : C EDA/Debug Tools : Xilinx ISE, VCS,Hspice,Libero,Rivera Pro. PROJECTS 1. Verification of ... - 2016 Nov 11
Engineer Design
Bengaluru, KA, 560001, India
... I have experience in verilog HDL, System verilog and writing test bench for digital circuits. I have also knowledge of UVM, ASIC verification and Physical Design concepts. ACADEMIC DETAILS Examination University Institute Year CGPA/% Bachelor of ... - 2016 Nov 09
... I have experience in verilog HDL, System verilog and writing test bench for digital circuits. I have also knowledge of UVM, ASIC verification and Physical Design concepts. ACADEMIC DETAILS Examination University Institute Year CGPA/% Bachelor of ... - 2016 Nov 09
Project Engineer
Bengaluru, KA, 560001, India
... TECHNICAL SKILLS Scripting : Basics of Shell, Perl Schematic & Layout Editor : Cadence(Virtuoso) Circuit Simulators : Spectre, B2Spice Physical verification : Assura (DRC, ERC, LVS) Hardware languages : VHDL, Verilog Operating systems : Windows, ... - 2016 Nov 08
... TECHNICAL SKILLS Scripting : Basics of Shell, Perl Schematic & Layout Editor : Cadence(Virtuoso) Circuit Simulators : Spectre, B2Spice Physical verification : Assura (DRC, ERC, LVS) Hardware languages : VHDL, Verilog Operating systems : Windows, ... - 2016 Nov 08
Project Power
Bengaluru, KA, 560001, India
... Board Of Secondary Education 2008 70 Programming Languages : C,VHDL & Verilog Simulation Soft wares :MATLAB,Xilinx,Cadence,DSCH2&MICROWIND Working knowledge of Microsoft word, Power point, Excel. Actively taken part in Organizing College Symposiums. ... - 2016 Oct 17
... Board Of Secondary Education 2008 70 Programming Languages : C,VHDL & Verilog Simulation Soft wares :MATLAB,Xilinx,Cadence,DSCH2&MICROWIND Working knowledge of Microsoft word, Power point, Excel. Actively taken part in Organizing College Symposiums. ... - 2016 Oct 17
Project Coordinator Technical
Bengaluru, KA, 560001, India
... 2008 10th NCERT Demonstration School, Mysore 59.80% 2006 Technical skills: Programming languages known: C, C++, embedded C,Verilog/VHDL, 8051 assembly Tool used: MPLAB, microC, Keil µVision,Proteus,MATLAB, Xilinx, Micro-Wind, DSCH,Atmel Flip,, Code ... - 2016 Oct 17
... 2008 10th NCERT Demonstration School, Mysore 59.80% 2006 Technical skills: Programming languages known: C, C++, embedded C,Verilog/VHDL, 8051 assembly Tool used: MPLAB, microC, Keil µVision,Proteus,MATLAB, Xilinx, Micro-Wind, DSCH,Atmel Flip,, Code ... - 2016 Oct 17
Engineer Test Cases
Bengaluru, KA, 560001, India
... manage and be a key player in strategic projects focused on operational improvement, and attain professional growth within these areas Summary Hand on experience in design verification and debugging of test cases in Verilog, System Verilog and UVM. ... - 2016 Oct 16
... manage and be a key player in strategic projects focused on operational improvement, and attain professional growth within these areas Summary Hand on experience in design verification and debugging of test cases in Verilog, System Verilog and UVM. ... - 2016 Oct 16
M.Tech (VLSI)Fresher
Bengaluru, KA, 560001, India
... Experience in writing RTL models in verilog. Good understanding of object oriented programming (OOP) concepts. Skilled in HVLs such as system verilog. Good knowledge of Digital Design concepts and FSM fundamental concepts. Knowledge on the concepts ... - 2016 Oct 16
... Experience in writing RTL models in verilog. Good understanding of object oriented programming (OOP) concepts. Skilled in HVLs such as system verilog. Good knowledge of Digital Design concepts and FSM fundamental concepts. Knowledge on the concepts ... - 2016 Oct 16
Engineer Test Cases
Bengaluru, KA, 560001, India
... Core Competency: Good knowledge of Verilog RTL coding Good exposure to VLSI technology by undergoing additional training in VLSI Implemented a VLSI a project during my post grad Good working knowledge of Linux, and C programming Good knowledge of ... - 2016 Oct 14
... Core Competency: Good knowledge of Verilog RTL coding Good exposure to VLSI technology by undergoing additional training in VLSI Implemented a VLSI a project during my post grad Good working knowledge of Linux, and C programming Good knowledge of ... - 2016 Oct 14
Test Project
Bengaluru, KA, 560001, India
... of a team that dynamically Works towards success and growth of the organization PROFESSIONAL SKILLS: Languages:, System Verilog,Verilog, VHDL, TCL/TK and C •5+ years of experience in Test plan creation, Modeling Test bench and test case coding. ... - 2016 Oct 05
... of a team that dynamically Works towards success and growth of the organization PROFESSIONAL SKILLS: Languages:, System Verilog,Verilog, VHDL, TCL/TK and C •5+ years of experience in Test plan creation, Modeling Test bench and test case coding. ... - 2016 Oct 05