B V V Kiran Kumar

Adamilli village, K.Kota mandal,

West Godavari district, Email: acxgzx@r.postjobfree.com

A.P, India – 534449 Mobile: +91-944*******

Objective

To secure a challenging position in an organization where I can apply my knowledge and skills in a team to make a significant contribution in the growth of the organization through which I can develop myself as a professional.

Skills

HDL: Verilog

HVL: SystemVerilog

Scripting Language: Perl

Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA

TB Methodology: UVM

EDA Tool: Questasim and ISE, Modelsim

Cadence Tool Suite (Virtuoso, Encounter, NC Launch, RC) Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional Coverage, Synthesis,

Static Timing Analysis.

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore

June 2015 – Feb 2016

Master of Technology, Vellore Institute of Technology, Chennai

VIT University, Tamil Nadu, India

Discipline: VLSI Design

CGPA: 7.28

Year of Passing: May 2015

Bachelor of Technology, Sasi Institute of Technology and Engineering, Tadepalligudem JNTUK University, Kakinada, India Discipline: Electronics & Communication Engineering Percentage: 70.02

Year of Passing: May 2013

Intermediate, Andhra Junior College, Kondapalli

Discipline: M.P.C

Percentage: 88

Year of Passing: May 2009

SSC, Z.P High School, Ponangi

Percentage: 73.83

Year of Passing: May 2007

Projects

[1] Router 1x3 – RTL design and Verification

Description: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2.

Responsibilities:

Architected the design

Implemented RTL using Verilog HDL.

Architected the class based verification environment using system Verilog

Verified the RTL model using SystemVerilog.

Generated functional and code coverage for the RTL verification sign-off

Synthesized the design

[2] AHB2APB Bridge IP Core Verification

HVL: System Verilog

TB Methodology: UVM

EDA Tool: Questasim

Description: The AHB to APB Bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses

Responsibilities:

Architected the class based verification environment in UVM

Verified the RTL module with single master and single slave

Generated functional and code coverage for the RTL verification sign-off

[3] CNTFETs based on ternary logic gates

Description: This paper presents Ternary logic is promising alternative to the binary logic, it is accomplished simple and energy efficient. It is a three valued logic. The CNTFET is a promising alternative to the bulk silicon transistor for low-power and high performance design due to its ballistic transport and low OFF-current properties. Extensive simulation results using Cadence Virtuoso are reported to show that the proposed ternary logic gates consume significantly lower power and delay than the previous resistive-load CMOS gates implementation.

Tools Used : Cadence Virtuoso

[4] Hardware Implementation of canonic signed digit recoding

Description: The implementation to convert a two’s complementary number into its canonic signed digit representation. In these CSD recoding circuits are functionally equivalent carriers H and K are described. They are computed in parallel reducing the critical path. They possess some properties which are used a minimizing the overall hardware implementation. They are computed using the power, area and gates, with this comparison CSD recoding has good performance.

Tools Used : Xilinx, Cadence RC, Cadence Encounter

[5] Hardware Implementation of CORDIC power of two Length DCT

Description: The Co-ordinate rotation digital computer (CORDIC) using different DCTs are four point, eight point and inverse eight point. By reusing uniform processing elements developed the architecture of the eight point CORDIC DCT. The uniform processing elements has two different types of PEs. The processing element (PE_1) has CSAs and CLAs. The processing element (PE_2) has different types of shifters, CLAs and registers. When compared with other known architectures, the proposed 8-point DCT architecture is more efficient. Power analysis and area estimation are performed for the designed architectures and then further power reduction is carried out using clock gating technique.

Tools used : Xilinx, Cadence RC, Cadence Encounter

Extra Curricular activities

Presented a poster titled Hardware Implementation of CORDIC power of two Length DCT at the Emerging Trends in Engineering and Technology symposium organized by the School of Electronics (SENSE), VIT Chennai

Publications

“Hardware Implementation of CORDIC power of two length DCT” in Indian Journal of science and technology, vol 8(25),IPL0449,October-2015.

“Hardware Implementation of Canonic Signed Digit Recoding” in IOSR Journal of VLSI and Signal Processing, Volume 6, Issue 2, Ver. I (Mar. -Apr. 2016), PP 00-00e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197

Personal Profile

Father’s Name : Bonthu.Baskara Rao

Date of Birth : 04-05-1992

Gender : Male

Nationality : Indian

Languages known : Telugu and English

Declaration

I here by declare that all the above information furnished by me is true to the best of my knowledge and belief.

Place: Name: B.V V Kiran Kumar

Date:

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