K. SAI RAMESWARI

D.No:*-*-***, Near Fort Gate acxgi0@r.postjobfree.com

Pithapuram-533450 https://in.linkedin.com/in/sairameswari Andhra Pradesh Contact no: +91-901*******.

CAREER OBJECTIVE

To work in a challenging environment, which provides opportunity to give out my best to the organization, upgrades my knowledge and improves my skill in Semiconductor industry. EDUCATIONAL PROFILE

2013-2015

M.Tech in VLSI Design from University college of Engineering Kakinada with 76.60%

2009-2013

B. Tech. in Electronics and Communication Engineering from Ideal Institute of Technology under JNTUK with 77.60%

2009 Intermediate from Sri Chaitanya Junior College, Kakinada with 87.20% 2007 10th Std. from Bharat High School, Pithapuram under SSC with 75 % ADDITIONAL QUALIFICATION

Trained in Design and Verification (QCDVE QSoCs Certified Design and Verification Engineering) from QSoCs Technologies.

TECHNICAL SKILLS

HDL & HDVL : Verilog & System Verilog

Verification Methodology : UVM.

Scripting languages : Basics of Perl& Shell.

Programming Languages : C

EDA/Debug Tools : Xilinx ISE, VCS,Hspice,Libero,Rivera Pro. PROJECTS

1. Verification of ETHERNET MAC.

Language: UVM.

Tools: Rivera Pro, Libero.

Description: The Ethernet MAC (Media Access Control), within the Data Link Layer of the OSI reference model. The MAC is the portion of Ethernet core that handles the CSMA/CD protocol for transmission and reception of frames. It performs Frame Data Encapsulation and Decapsulation, Frame Transmission, and Frame Reception.

Role:

Took the RTL from open cores and analyzed.

Prepared the test plan.

Prepared the test bench architecture.

Test cases were verified.

2. Design and Verification of UART-APB.

HDL: Verilog HDL.

Verification Methodology: UVM.

Tools Used: Libero, Rivera Pro.

Description: A Universal Asynchronous Receiver / Transmitter (UART) is responsible for performing the main task in serial communications with computers. Advanced Peripheral Bus

(APB) is an interface defines in the advanced Microcontroller Bus Architecture (AMBA) and widely used as on-chip bus in system on-chip (Soc) designs. Design

Analyzed the specifications of UART-APB

Prepared micro-architecture for the same

Designed RTL of each sub modules in Verilog HDL

Direct testing of each sub modules was done.

Combined all the sub modules into a final module

Simple Verilog test bench created for the module and verified

Total design was completed in 1 month.

Verification

Took the RTL of UART-APB and analyzed its functionality

Prepared the test plan

Prepared the test bench architecture

Created the test environment in System Verilog

Methodology used is UVM.

All the test cases and corner cases were verified. 3. Design and Verification of Asynchronous FIFO.

HDL: Verilog HDL.

Tools Used: Libero, Rivera Pro.

Description: This project focuses on design and verification of Asynchronous FIFO which is used in preventing meta-stable state when a data is transmitting from high speed module to low speed module Synchronization of FIFO pointers into the opposite clock domain is safely accomplished using Gray code pointers. Asynchronous FIFO is designed in Verilog HDL and simulated using Rivero Pro.

Role:

Prepared micro-architecture for Asynchronous FIFO.

Designed RTL in Verilog HDL

Simple Verilog test bench created for the module and verified 4. Design of AXI4 Slave Interface Memory Controller for SoC Applications. (Academic Project)

HDL: Verilog HDL.

Tools Used: Synopsys VCS.

Description: The project involves the design of (Study,Design RTL coding, Simulation, Synthesis) implementation of AMBA AXI interface with memory controller is targeted at high performance, high frequency system designs and includes a number of features that make it suitable for a high speed submicron interconnects using Synopsys tools. Role:

Prepared micro-architecture.

Designed RTL in Verilog HDL

Simple Verilog test bench created for the module and verified. STRENGTHS

Willingness to learn.

Ability to work in a team.

Hard working

DECLARATION

This is to certify that all the information provided above are true to the best of my knowledge. Place:

Date:

(K.Sai Rameswari)

Contact this candidate