RESUME

Mo. +91-888*******

RAVI DORAI Email : acw1x5@r.postjobfree.com

Career Objective:

To be associated with a semiconductor industry that provides me boundless growth opportunities and exposure to cutting-edge technologies and learning possibilities. Core Competency:

Good knowledge of Verilog RTL coding

Good exposure to VLSI technology by undergoing additional training in VLSI

Implemented a VLSI a project during my post grad

Good working knowledge of Linux, and C programming

Good knowledge of RTL verification with the coding of SystemVerilog& UVM.

Good understanding of verification methodlogy especially in Universal Verification Methodology

Hands on experience in Coverage Driven Verification (Functional Coverage and Code Coverage).

Coverage using SystemVerilog and UVM

Basic knowledge of UART, I2C, SPI and Ethernet Protocols

Good analytical skills to debug the syntactical and logical errors

Basic knowledge of Shell and Perl scripting

Good knowledge of ASIC Design Flow

Hands on experience in the Cadence NCSIM, Questa sim, Xilinx ISE, Model sim, Rivera Pro.

Work Experience:

Currently am working in [Aug -18th-2016 to till date] Aquantia Semiconductor India Private Limited as a DDV (Digital Design &Verification) project intern.

8 months Project intern experience on ASIC Design & and Verification at Maven Silicon Softech Pvt ltd, Bangalore.

6 months of Advanced VLSI Design and Verification Course from Maven Silicon Softech Pvt. Ltd. Bangalore.

VLSI Domain Skills:

HDL : Verilog, VHDL.

HVL : SystemVerilog

Verification Methodologies : Coverage Driven Verification Assertion BasedVerification

TB Methodology : UVM,OVM

Bus Protocol : AMBA AXI, AHB,APB

Serial Protocol : SPI, I2c, UART

EDA Tool: : Questa sim and Xilinx ISE,Model sim,

Domain: : ASIC/FPGA Design Flow, Digital Design

Knowledge RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis,

Scripting language : Perl, Shell (Makefile)

Programming language : c, c++.

Professional Qualification:

M-tech in VLSI Design System from SVCET Engineer college, chittoor under JNTU Anathapuram University [2013-2015] With the Aggregate of 9.24 (C.G.P.A).

B-tech in Electronics &Communication Engineer from VEMU Engineer College, chittoor under JNTU Anathapuram University [2009-2013] With the Aggregate of 71%.

PUC from Sri Vivekananda junior College, chittoor under the Board of A.P Hyderabad [2007-2009] With the Aggregate of 77%.

SSLC from Govt boy’s higher secondary school, paradarami under the board of Thirupattur [2007] with the Aggregate of 70%.

VLSI Projects:

Modules worked on Activities

Design and verification of AMBA-

(AHB-APB)Bridge protocol

Role: Design &Verification

HDL:Verilog

HVL: System-Verilog

EDA Tools: Questasim

Methodology: UVM

Designed an AHB to APB Bridge which

communicate between high frequency AHB

Components (master) and low frequency APB

components (slave).

It supports read/write operations as well as single, increment and burst data transfer.

Developed class based verification environment for multiple masters multiple slaves (maximum 8

masters, 8 slaves) using UVM.

Implemented interconnect module for arbitration.

Developed Driver functionality for Master and

Slave

Developed Monitor, Scoreboard, master sequence,

virtual sequence

Master supported features like OK, RETRY,

ERROR and SPLIT Response

Developed Verification Plan and Testcases

Functional coverage check

AMBA-AXI 3/4 UVC

Role: Verification

HVL: System-Verilog

EDA Tools: Questasim

Methodology: UVM

Understood the AXI Protocol Specification

Prepared the Verification Plan

Single Master and Single Slave VIP

Burst mode supported are Increment, Wrap and

Fixed

Data transfer for Aligned And Unaligned Address

Implemented Test cases

Constrained Random Stimulus Generation using

Sequences.

Functional and Code coverage

UART Master Core

Role: Verification

HVL : SystemVerilog

Methodology: UVM

EDA Tools: Questasim 10.0b

Understood the complete UART Protocol

Planned the Verification Architecture

UVM Based Environment (UART Core to UART

Core Communication)

Implemented Test cases for verification of IP

Developed coverage model and Scoreboard for the

IP

Features Verified

1. Loop back mode

2. Full duplex mode

3. Half duplex mode

4. Break, Frame, Overrun and Parity Error

SPI Controller

Role: Verification

HVL: System-Verilog

EDA Tools: Questasim

Methodology: UVM

Good Knowledge of SPI Protocol

Generated UVM Based Environment (Single Master

- Multiple Slaves)

Random Stimulus Generation

Implemented Test cases

Features Verified

1. Full Duplex Mode

2. Different Mode based on clock phase and

polarity

3. Various character lengths

4. LSB and MSB Data transmission

Academic Projects:

Design and verification of

ROUTER(1X3) protocol

Role: Design &Verification

HDL:Verilog

HVL: System-Verilog

EDA Tools: Questasim

Methodology: UVM

Router is a device that forwards data packets

between computer networks. It is an OSI layer 3

routing device.

Based on a predefined protocol, this router drives an incoming packet to any one among the three

output channels based on the address field

contained in the packet header.

Designed RTL using Verilog.

Developed Architecture of Verification

Enivironment using SV &UVM.

Developed of various test cases & verified RTL.

Generated Functional & Code Coverage for

Verification Signoff.

Parking Guidance and

Information System Based on

Wireless Sensor Network

Tool kit :8051

Our aim of in this project is we can control the parking system through our PC by receiving

parking slot states from zigbee protocol

communication.

Here we place IR sensors, whenever vehicle

present/leave IR activated means slot full others wise slot empty.

Personal Details:

Name : D.RAVI

Nationality : Indian

Language Known : English, Telugu,Tamil,Kanada,Hindi

Date of Birth : 04th Jun,1992

Hobbies : Playing cricket, Reading book, Solving Puzzles

Address : “Keshava PG, btm2 stage, madiwala Road, Bangalore-560076

Declaration:

I hereby declare that the information given here with is correct to best of my knowledge and I will responsible for any discrepancy. Place: Bangalore D.RAVI

DATE:

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