Resume

Ch.chaitanya siva kumar

+** -789*******

acw2zr@r.postjobfree.com Address:

S/o chenchaiah,

Bapuji nagar,near udayagiri road,

Kavali,Nellore(dt),

Andhra Pradesh,Pin-524201.

Objective

Result oriented and dynamic professional with wide exposure in ASIC verification. Sound knowledge on verification tools and logic design. Looking for a job in a prestigious organization to consult, manage and be a key player in strategic projects focused on operational improvement, and attain professional growth within these areas

Summary

Hand on experience in design verification and debugging of test cases in Verilog, System Verilog and UVM.

Good understanding of AMBA AHB–lite and APB Protocols.

Completed multiple projects using System Verilog language.

Well built knowledge of different design and verification method using Verilog.

Hands on experience in QUESTA Sim(Mentor Graphics), NCSim (Cadence), Rivera, Model Sim debugging tools.

Excellent communication skills, both written and verbal.

An ability to build rapport and trust quickly with work colleagues.

Able to prioritize tasks and workloads in order of importance.

Professional Experience

ASIC DESIGN VERIFICATION ENGINEER ( oct 2015 – till date)

VerifWorks, a CVC PVT. LTD Venture – Bangalore, Karnataka

Technical Skills

HDL: Verilog

HVL:System Verilog,UVM(Universal Verification Methodology)

Tools: Questa-Sim,Nc-sim(Cadence),Riviera,Model-Sim.

Operating System: UNIX/LINX,Windows.

Subject:Digital Electronics.

Project Experience

Design Verification of APB-SPI in UVM

Roles and Responsibilities:

oDeveloped complete verification environment for APB-SPI with UVM.

oPlayed active role in simulation, verification coding, and review of module

oUsed Constrained Random Verification

oTool Used: Riviera

Design Verification of AMBA 3 AHB-Lite slave using UVM

Roles and Responsibilities:

oCreated verification environment for AMBA 3 AHB-Lite with UVM. o Development of Driver and Monitor .

o Tool Used: Riviera

Design Verification of AMBA 2.0 APB

Roles and Responsibilities:

oDevelopment of RTL and tested in linear testbench.

oCreated Verified in System verilog environment and UVM environment.

oTool Used: Model Sim/Riviera

Design Verification of FIFO in UVM

Roles and Responsibilities:

oThe module design and verified in the linear and System verilog test-bench.

oIn UVM created the skeleton for the FIFO and written the test cases.

oTool Used: Questa-Sim

Academic Projects

BE : Project Name: Wireless Temperature Monitoring System

Team size : 4

Description : we monitoring the temperature from one stage to the other stage by using

the “Zigbee technology” .In this we are using the temperature sensor (LM35) and

Arduino (ATmega 328).

There are two stage transmitter stage and the receiver stage by interface the zigbee and the

Arduino.so that we can transferring the data of temperature sensor(LM35) in transmitter to

receiver stage by the wireless technology.This temperature sensor can detecting range is –

55 C to 150 C.

Education

oCompleted B.E (Electrical & Electronics) from CMRIT Engineering College, Bangalore (53%).

oCompleted Intermediate (M.P.C) from Narayana Junior College,Nellore (75%).

oCompleted SSC from St’anns Eng Medium high School,Kavali ( 70%) .

Bangalore ch.chaitanya siva kumar

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