RESUME

Email id:acw3dl@r.postjobfree.com

Ph no:801-***-****,812-***-****

To work in a healthy, innovative and challenging environment extracting the best out of me, which is conducive to learn and grow at professional as well as personal level thereby directing my future endeavours as an asset to the organization.

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Degree

College/School

Board/University

Year Of Passing

Percentage

M. Tech Specialization

in VLSI

Koneru Lakshmaiah Education Foundation.

KL UNIVERSITY

2016

8.83CGPA

B. Tech Specialization

in ECE

Tenali Engineering College,Anumarlapudi.

JNTU, Kakinada

2014

70

Intermediate

NRI Jr.College

Guntur.

Board of Intermediate Education

2010

76

S.S.C

ZPHigh School, Angalakuduru.

Board Of Secondary Education

2008

70

Programming Languages : C,VHDL & Verilog

Simulation Soft wares :MATLAB,Xilinx,Cadence,DSCH2&MICROWIND

Working knowledge of Microsoft word, Power point, Excel.

Actively taken part in Organizing College Symposiums.

PROJECT - 1

Title : Main Project on “GREEN-BEE USING ZIGBEE TECHNOLOGY OVER A COMPER COMPUTER"

Language : C Language,Verilog

Tool Used: Keil Software- Embedded Development Kit.

Description : The Main Intentions of doing this project is to measure water level, humidity, temperature. If the water level was exceeded then the motor detects it and stop automatically. This can be done by using zigbee technology.

S.NO

SOFTWARE TOOL USED

PROJECT TITLE

1.

XILINX

Smartphone Interface FPGA Interface Using HC05 Module.

2.

DSCH2 & MICROWIND

Design and Implantation of Transceiver.

3.

CADENCE ANALOG

1) CMOS Digital Gates with Dual Threshold Transistor Stacking Technique.

2) Design and Analysis of the Mixer.

PROJECT - 2

Title : Variable Input Delay CMOS Logic For Low Power Design

Tool Used : Cadence Design

Description : In this paper we are reducing the power dissipation by using static and dynamic power dissipations. The CMOS logic circuits we are giving the input producing the output at some delay so we are getting the glitches. The reducing the glitches in order to reducing the power dissipation and increasing the speed of operation of the CMOS circuits.

PROJECT – 3

Title : Dynamically Reconfigurable Smart Traffic System for Accident Rescue Opertaion.

Language : C Language,Verilog

Tool Used : Xilinx Platform Studio

Description : In this model represents real-time traffic conditions, When emergency vechicle is moving on a confined traffic path. Reconfigurable smart traffic system architecture consists of vibration sensors and MEMS sensor which are interfaced to FPGA. When a vehicle collision is enumerated the vibration sensors in the vehicle senses and sends the GPS location of vechicle to the ESC(Emergency service centre). Remote location informtion is communicated to ESC from VSMAS(Vibration sense message alert system) through GSM and GPS interface. Pre recorded message along with remote location details are communicated to ESC through FPGA. VSMAS Module is programmed in Xilinx Platform Studio – Embedded Development Kit.

Other Achievements:

Participated in paper presentation.

Participated in poster presentation.

Comprehensive problem solving abilities and analytical skills.

Hard working.

Good verbal and written communication skills.

Team building abilities.

Adaptability to situation, confidence and optimism.

Playing games.

Gardening.

Listening music.

Name : Bodduluri Rajitha

Date of Birth : 10-08-1993

Gender : Female

Father Name : Mr. B.Subbaa Rao

Languages Known : English, Telugu

Nationality : Indian

Address : H-NO:1-54

Gudivada(post), Tenali(M.D),

Guntur(DIST), Pin Code-522307.

I am confident that I shall strive and succeed in the position applied to the satisfaction of my superiors and justice the assignments entrusted on me. I declare that the information furnished above is true to the best of my knowledge.

Place: Gudivada Name of the Candidate

Date: (B.Rajitha)

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