KAKARLA BHARATH KALYAN

Email:acxe1u@r.postjobfree.com Mobile: +917*********

CAREER OBJECTIVE

Seeking a career as VLSI ENGINEER within an organization, where I can contribute my skills for organization’s success and synchronize myself with new technology while being resourceful, innovative and flexible.

TECHNICAL COURSE SUMMARY

Pursuing Post Graduate Diploma in VLSI Design & Technology using Cadence EDA Tools at Industrial Training and Research Institute (ITRI), Bangalore.

TECHNICAL SKILLS

Scripting

:

Basics of Shell, Perl

Schematic & Layout Editor

:

Cadence(Virtuoso)

Circuit Simulators

:

Spectre, B2Spice

Physical verification

:

Assura (DRC, ERC, LVS)

Hardware languages

:

VHDL, Verilog

Operating systems

:

Windows, Linux (REDHAT)

Others

:

Command line interface (CLI), some basics in CMOS, knowledge in digital design, understanding full custom design flow

EDA TOOL EXPOSURE

CADENCE (NcVerilog, Simvision, RTL Compiler, SOC Encounter, VIRTUOSO & ASSURA)

AREAS OF INTEREST

Digital Logic Design

Front end Verilog coding and verification

ACADEMICS PROJECTS

PROJECT TITLE: DESIGN AND LAYOUT OF STANDARD CELLS.

Description: In this project we have implemented basic gates like Inverter, NAND, NOR, AND, OR, XOR, XNOR. The modules are verified by checking different parameters such as DRC, ERC, and LVS.

EDA TOOL: Virtuoso & Assura. TECHNOLOGY NODE: GPDK 180nm

PROJECT TITLE: HIGH PERFORMANCE ARITHEMATIC LOGIC ADITION USING CADENCE TOOL.

Description: In this project is to design high performance arithmetic circuits which are faster and have lower power consumption using a new dynamic logic family of CMOS and to analyse its performance for sequential circuits and effects upon cascading. This new dynamic logic family is known as Feedthrough logic. It has two basic structures: high speed (HS0) and low power (LP0). We compare a set of ripple carry adders 4 bit and 16 bit in domino logic with the two basic structures derived. The effects upon cascading are analyzed by using a 4-bit register. In this circuit being edge triggered, the major advantage of this logic which is observed upon cascading cannot possibly be observed for sequential circuits. So even though the circuit can be optimized by feedthrough logic, this logic is not preferred for sequential circuits.

EDA TOOL: Virtuoso & Assura. TECHNOLOGY NODE: GPDK 180nm

PROJECT TITLE: HAND GESTURE CONTROLLED ROBOTA USING ACCELEROMETER.

Description: In this project we are going to control a robot wirelessly using hand gestures. This is an easy, user-friendly way to interact with robotic systems and robots. An accelerometer is used to detect the tilting position of your hand, and a microcontroller gets different analogue values and generates command signals to control the robot. This concept can be implemented in a robotic arm used for welding or handling hazardous materials, such as in nuclear plants.

Hardware: ATmega 8 Programming Languages: Embedded C

EDUCATIONAL QUALIFICATION

Degree

Institution

Board/

University

Year of Completion

Percentage Post Graduate Diploma

VLSI design

ITRI

2016

-

B Tech

(ECE)

Sri Krishnadevaraya University College of engineering and technology

SKUA

2016

64.68%

Intermediate (MPC)

Sri Chaitanya Jr. College, Vijayawada

Board of Intermediate Education

2012

70.9%

Secondary School Certificate

Sri Saraswathi vidhya mandiram, Kadiri

Board of Secondary Education

2010

70.66%

ACHIEVEMENTS

Secured 1st prize in FACE PAINTING organized in SRI KRISHNADEVARAYA UNIVERSITY COLLEGE OF ENGINEERING AND TECHNOLOGY.

PERSONAL DETAILS

Father’s Name

:

K. DAMODARA NAIDU

Date of Birth

:

08/08/1995

Gender

:

Male

Nationality

:

Indian

Known Languages

:

English, Telugu, Hindi, Kannada

Hobbies & Interests

:

Playing sports (Cricket, Caroms, Chess, Shuttle), Cooking, reading books and components identifying in circuits etc.

DECLARATION

I hereby declare that the above mentioned details are true to the best of my knowledge.

Place: Bangalore

Date: K. Bharath Kalyan

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