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Test Project

Location:
Bengaluru, Karnataka, 560001, India
Posted:
October 05, 2016

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Resume:

Samba Siva Rao.D

Mobile: +**996-***-**** Email:acww8w@r.postjobfree.com

Objective

•To pursue a challenging role in designing ASIC/FPGA based verification, to utilize my

Knowledge and skills in hardware design and is a member of a team that dynamically

Works towards success and growth of the organization

PROFESSIONAL SKILLS:

Languages:, System Verilog,Verilog, VHDL, TCL/TK and C

•5+ years of experience in Test plan creation, Modeling Test bench and test case coding.

•Working experience on Verification Methodologies OVM/UVM.

•Working experience on High Speed Serdes verification using specman.

•Involved in verification of high speed controllers like DDR, NAND Flash and OTP controller.

•Involved in verification of high speed bus protocols like PCIe-DMA, AXI and AHB.

•Working experience on formal verification using Cadence Jasper tool.

•Working experience on IP Low power verification using CPF.

•Working experience on gate level simulation (GLS).

•Code coverage analysis using vmanager.

•Familiar with FPGA flow and ASIC flow.

•Implementation of low speed protocols like I2C and SPI.

PROFESSIONAL EXPERIENCE:

S.No

Company Name

Duration

1

Cadence Design Systems, Inc.

June,2015 to till date

2

CYIENT Ltd (InfoTech Ltd)

September,2014 to June,2015

3

CoreEL Technologies Ltd

July,2009 to September 2014

Project7: Serdes IP and Low power verification

Role: test case coding

Methodology: UVM

Synopsis:

•Created CPF for small IP block.

•Coded Testcases.

•Developed UVC’s for PMA.

•Verified low power strategies for SERDES.

Tools Used: Cadence

Project6: PLL IP verification

Role: Test plan creation, Test bench coding and test case coding.

Methodology: UVM

Synopsis:

•Created Testplan to verify PLL.

•Developed re-usable and configurable test bench development using SV+UVM.

•Coded Testcases.

Tools Used: Cadence

Project5: SMBus VIP

Role: Test plan creation, Test bench coding and test case coding.

Methodology: UVM

Synopsis:

•Created Testplan to verify SMBus VIP.

•Developed re-usable and configurable test bench development using SV+UVM.

•Coded Testcases.

Tools Used: Cadence

Project4: OTP Controller verification

Role: Test plan creation, Test bench coding and test case coding.

Methodology: UVM

Synopsis:

•Created Testplan to verify OTP Controller.

•Developed re-usable and configurable test bench development using SV+UVM.

•Coded Testcases.

Tools Used: Cadence

Project 3: NAND Flash Controller

Role: Test plan creation, Test bench coding and test case coding.

Methodology: UVM

Synopsis:

•Created Testplan to test various features supported by NAND flash controller.

•Developed re-usable and configurable test bench development using SV+UVM.

•Coded Testcases.

Tools Used: Cadence

Project 2: PCIe-DMA Controlller

Role: Coding

Methodology: OVM

Synopsis:

•Involved in coding of re-usable OVC of DDR and PCIe-DMA.

•Involved in test case coding.

Tools Used: Cadence and Modelsim

Project 1: AMBA protocol verification

Role: OVM

Methodology: OVM

Synopsis:

•Involved in coding of re-usable OVC of AXI and AHB.

•Involved in test case coding.

Tools Used: Cadence and Modelsim

Tools:

•Cadence NC-SIM,RTL Compiler (RC), HAL (Lint), STA, LEC

•Xilinx Tools, Mentor Graphics.

Education:

B.E (E&C) from IETE --- CGPA 7.8

PG Diploma in VLSI Design --- Grade – A

Diploma in IEE in Institute of Electronics --- 90.1%

SSC --- 81.16%

Personal Details

Name : Samba Siva Rao.D

DOB : 11-12-1990

Marital Status : Single

Declaration:

I hereby declare that the statements made above are true, complete and correct to the best of my knowledge and belief.

Samba Siva Rao.D



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