UPPUTURI NEELIMA Contact : +91-895*******
Email : acw2x0@r.postjobfree.com
Objective :
A challenging career in ASIC/EDA/VLSI industry where my “can-do” attitude, current experience and skill sets can be used and grow professionally while helping Organization benefit from my learning.
Core competency :
Basic knowledge of ASIC/FPGA Design Flow.
Experience in writing RTL models in verilog.
Good understanding of object oriented programming (OOP) concepts.
Skilled in HVLs such as system verilog.
Good knowledge of Digital Design concepts and FSM fundamental concepts.
Knowledge on the concepts of UART, AMBA AHB protocols.
Knowledge on the concepts of Asynchronous FIFO, Synchronous FIFO,VGA.
Basic knowledge of IC fabrication techniques.
Good understanding of MOS fundamentals.
Basic knowledge of C.
Education :
Degree
Discipline
College/ University
Year of passing
Aggregate
M.Tech
VLSI
KL University
2016
8.9(CGPA)
B.Tech
E.C.E
Chalapathi Institute of Technology
2013
72
Inter
M.P.C
Vikas Mahila Junior College
2009
91.5
SSC
Secondary Education
Vignan Public School
2007
86
Professional Qualification :
Currently Doing Internship at SION Semiconductors Pvt.Ltd from December 2015,Bangalore.
VLSI Domain Skill Set :
HDL : Verilog
HVL : System Verilog
EDA Tools : Xilinx ISE 14.2, Questasim 10, Modelsim
Domain : ASIC/FPGA Design flow, digital design methodologies
Knowledge : RTL Coding, FSM based Design, Simulation, Synthesis
VLSI Projects:
UART- Design
HDL : Verilog
HVL : System Verilog
EDA Tools : Modelsim, Questasim
Job Profile/Responsibility :
Implemented The UART design using Verilog HDL
Built the class based environment using System Verilog
Verified the UART Design using Verilog HDL
ASYNCHRONOUS FIFO Design and Verification
HDL : Verilog
EDA Tools : Modelsim
Job Profile/Responsibility :
Implemented The Asynchronous FIFO design using Verilog HDL
Verified the Asynchronous FIFO Design using Verilog HDL
FIFO – Design and Verification
HDL : Verilog
HVL : System Verilog
EDA Tools : Modelsim, Questasim
Job Profile/Responsibility :
Implemented the using Verilog HDL
Verified the FIFO Design using Verilog HDL
Built the class based design environment using System Verilog
Developed Driver, Monitor, Scoreboard functionality
FIFO was verified in System Verilog with the use of write, read, write and read test cases.
M.Tech Project :
Title : “Data Encryption and Decryption using Reed-Muller Techniques”.
Description : Secure and error free data transmission plays an important role in communication. The main objective of this project is to encode and then decode the data using distinct Reed-Muller
techniques such as PPRM, NPRM, and FPRM. Here we compare these techniques in terms of power dissipation. Among those FPRM gives less power dissipation.
Title : “A Low Power Schmitt Trigger Design using SBT technique in 180nm CMOS Technology.
Description : The main objective of the project is to determine the effect of source voltage and load capacitance on the performance of CMOS Schmitt Trigger circuit with self-bias transistor technique which was used to reduce power. The CMOS Schmitt Trigger circuit was modified by designing the transistors aspect ratio on the basis of conventional CMOS Schmitt Trigger and it is implemented using CADENCE Virtuoso.
Research Publication :
Upputuri Neelima, Fazal Noorbasha “International Journal of Engineering & Technology (IJET)”,vol.8, no.1,February 2016.
Personal Profile
Name : Upputuri Neelima
Date of Birth : 25-03-1992
Address : Turagavaripalem, Amaravathi (M), Guntur (Dt), AP
Father Name : Balagangadhar Reddy
Nationality : Indian
Sex : Female
Languages Known : English,Telugu
I hereby declare that all the information given above is good and true upto my knowledge.
DATE :
PLACE : Bangalore (U.Neelima)