| Resume alert | Resumes 171 - 180 of 513 |
Analog, Mixed Signal and High-speed layout
San Jose, CA
... Responsible for floor planning, block placement, signal routing, power plans & integration process, worked on Cadence Virtuoso 12.1, CCAR, Assura LVS and RCX, and Calibre and Hercules DRC, LVS, ERC, Density, HV, ESD, Latchup, Antenna Excellent ... - 2017 Jul 12
... Responsible for floor planning, block placement, signal routing, power plans & integration process, worked on Cadence Virtuoso 12.1, CCAR, Assura LVS and RCX, and Calibre and Hercules DRC, LVS, ERC, Density, HV, ESD, Latchup, Antenna Excellent ... - 2017 Jul 12
C,C++, Verilog, Python
San Jose, CA
... PROJECTS IFFT using Butterfly Matrix [Verilog HDL] Spring’17 Designed and implemented 32-point IFFT using radix-2 butterfly matrix in Verilog VCS simulation, Gate level simulation and NC Verilog simulation were performed using Cadence SimVision tool ... - 2017 Jul 07
... PROJECTS IFFT using Butterfly Matrix [Verilog HDL] Spring’17 Designed and implemented 32-point IFFT using radix-2 butterfly matrix in Verilog VCS simulation, Gate level simulation and NC Verilog simulation were performed using Cadence SimVision tool ... - 2017 Jul 07
Network Engineer Manager
Fremont, CA
... May, 2002 - March 2016 Verisity Inc./Cadence Design Systems Lead Telecom Engineer Designed,documented, and maintained 50 site worldwide telecom infrastructure. Performed PBX, phone, andPolycom video conferencing support and management. VM Server ... - 2017 Jul 05
... May, 2002 - March 2016 Verisity Inc./Cadence Design Systems Lead Telecom Engineer Designed,documented, and maintained 50 site worldwide telecom infrastructure. Performed PBX, phone, andPolycom video conferencing support and management. VM Server ... - 2017 Jul 05
VLSI Digital Design Engineer
Santa Clara, CA
... Cadence tools Virtuoso and Assura. VHDL/Verilog Design, Implementation and Synthesis on both Altera and Xilinx Platform. Verilog synthesis, placement and routing and debugging using Synopsys VCS and analysis using design vision. WORK EXPERIENCE: ... - 2017 Jul 03
... Cadence tools Virtuoso and Assura. VHDL/Verilog Design, Implementation and Synthesis on both Altera and Xilinx Platform. Verilog synthesis, placement and routing and debugging using Synopsys VCS and analysis using design vision. WORK EXPERIENCE: ... - 2017 Jul 03
Design Engineer
San Jose, CA
... • Two Stage Operational Transconductance Amplifier design on 180nm technology node (Apr.2016-May.2016) A two-stage amplifier was designed using 180nm technology on Cadence virtuoso with Phase Margin- 72.8 Degrees, Closed Loop Gain~2, Open Loop Gain ... - 2017 Jul 03
... • Two Stage Operational Transconductance Amplifier design on 180nm technology node (Apr.2016-May.2016) A two-stage amplifier was designed using 180nm technology on Cadence virtuoso with Phase Margin- 72.8 Degrees, Closed Loop Gain~2, Open Loop Gain ... - 2017 Jul 03
Product Development Engineer
San Jose, CA
... *Word, Excel, Outlook, Power Point, AutoCAD, Cadence Allegro Electronics engineering technician 2000 - 2006 *I was responsible for creating wire bond drawings for substrate designs for Intel wireless products which included all collaterals drawings, ... - 2017 Jun 28
... *Word, Excel, Outlook, Power Point, AutoCAD, Cadence Allegro Electronics engineering technician 2000 - 2006 *I was responsible for creating wire bond drawings for substrate designs for Intel wireless products which included all collaterals drawings, ... - 2017 Jun 28
Design Engineer Electrical Engineering
Mountain View, CA, 94040
... Tools: OrCAD, Altium, LabView, SOLIDWORKS, AutoCAD Inventor, FreeCAD, TI Code Composer Studio, Atmel Studio, R-Studio, Cadence Allegro-SI, HyperLynx, ActelLibero, PADS, MatLab, ModelSim. Equipment: Oscilloscope, Logic Analyzer, Network Analyzer, ... - 2017 Jun 28
... Tools: OrCAD, Altium, LabView, SOLIDWORKS, AutoCAD Inventor, FreeCAD, TI Code Composer Studio, Atmel Studio, R-Studio, Cadence Allegro-SI, HyperLynx, ActelLibero, PADS, MatLab, ModelSim. Equipment: Oscilloscope, Logic Analyzer, Network Analyzer, ... - 2017 Jun 28
ASIC Design Engineer
Sunnyvale, CA
... Institute of Technology 2008 – 2012 Bachelor’s Degree in Electronics Engineering, 3.7 GPA Mumbai, India SKILLS: EDA Tools : QuestaSIM, Cadence-Virtuoso, PSPICE, Altera Quartus 13.0, ModelSIM, Matlab, Atalanta (ATPG) Programming Languages: C, C++, ... - 2017 Jun 27
... Institute of Technology 2008 – 2012 Bachelor’s Degree in Electronics Engineering, 3.7 GPA Mumbai, India SKILLS: EDA Tools : QuestaSIM, Cadence-Virtuoso, PSPICE, Altera Quartus 13.0, ModelSIM, Matlab, Atalanta (ATPG) Programming Languages: C, C++, ... - 2017 Jun 27
Digital/Hardware Engineer
Fremont, CA, 94537
... TECHNICAL SKILLS Development Tools: MICROWIND, Magic, Keil, SPICE Simulation, Multi2Sim, ModelSim, Ouartus II, QuartusLite 16.0(Altera), TCAD(Silvaco), Xilinx ISE 14.2, Cadence, ECAD, Proteus, Eclipse, GUI Interface, MIT App Inventor, Eagle, OrCAD, ... - 2017 Jun 24
... TECHNICAL SKILLS Development Tools: MICROWIND, Magic, Keil, SPICE Simulation, Multi2Sim, ModelSim, Ouartus II, QuartusLite 16.0(Altera), TCAD(Silvaco), Xilinx ISE 14.2, Cadence, ECAD, Proteus, Eclipse, GUI Interface, MIT App Inventor, Eagle, OrCAD, ... - 2017 Jun 24
Logic Design, Digital Design, RTL Design, Verification.
San Jose, CA
... CAD Tools: Synopsys VCS, Synopsys Design Compiler, GTKWave, Altera Quartus, Xilinx Vivado, Cadence Virtuoso ACADEMIC AND RESEARCH PROJECTS Network on Chip Bus using SoC Architecture and Network Topology [System Verilog, UVM] May 2017 Implemented a ... - 2017 Jun 12
... CAD Tools: Synopsys VCS, Synopsys Design Compiler, GTKWave, Altera Quartus, Xilinx Vivado, Cadence Virtuoso ACADEMIC AND RESEARCH PROJECTS Network on Chip Bus using SoC Architecture and Network Topology [System Verilog, UVM] May 2017 Implemented a ... - 2017 Jun 12