VLSI Digital Design Engineer
Resume:
Aakash Sarang
San Jose, CA
https://www.linkedin.com/in/aakash-sarang-50957aa3 ac04po@r.postjobfree.com
OBJECTIVE:
Actively seeking an opportunity in the field of High Tech Engineering where I can put my engineering skills into practice & develop myself along with the development of the organization. ACADEMICS:
MS in Electrical Engineering GPA: 3.350
San Jose State University, San Jose, CA August 2015 - May 2017
Bachelor of Engineering in Electrical Engineering GPA: 3.860 Gujarat Technological University, India June 2011 - May 2015 TECHNICAL PROFICIENCY:
Basics of C Language
Matlab, Simulink with both Windows/UNIX environments.
Basics of HTML and Python
Programmable Logic and FPGA architecture.
AMBA AXI, AHB, APB, UART, UVM
Basics of PLC Ladder Programming.
Cadence tools Virtuoso and Assura.
VHDL/Verilog Design, Implementation and Synthesis on both Altera and Xilinx Platform.
Verilog synthesis, placement and routing and debugging using Synopsys VCS and analysis using design vision. WORK EXPERIENCE:
COTMAC ELECTRONICS PVT.LTD. - Intern June 2014 - July 2014
Designed professional documentation for products.
Developed designs for Programmable Logic Controller for drives.
Demonstrated designing skills in Industrial Automation.
Successfully performed failure Analysis and troubleshooting in Industrial Drives. ACADEMIC PROJECTS:
Implementation of handwritten digits recognition system on FPGA using artificial neural network using python.
[ System Verilog, Verilog, Altera Quartus, Python, Tensorflow ] The ANN of four layers was implemented in python to use method of deep learning for the problem of recognition of handwritten digits and the system was tested to work correctly on python and on FPGA along with touch screen to use it interactively for handy mathematical applications.
A system verilog block of CRC detecting errors in 32 bit data. [ System Verilog, Synopsys VCS, UVM, Toshiba 0.18 um ]
Successfully designed and verified operation of the cyclic redundancy check using checksum for both 32bit data transfer and 16 bit data transfer using system verilog and TOSHIBA technology standard cell library.
A system verilog block of bidding arbiter that handles master slave architecture. [ System Verilog, Synopsys VCS, UVM]
Designed and verified proper communication between master and slave blocks using the bidding arbiter technique of arbitration which is used in communication links.
NIOS II fully pipelined architecture. [ Verilog, Synopsys VCS, UVM ] Successfully implemented and analyzed the performance of verilog subset of fully pipelined NIOS II architecture and verified using sample benchmark programs which use data sequence in such a way to exercise data dependencies in pipelines.
Low pass filter on a minimal NIOS II system with and without using hardware accelerator. [ Verilog, Altera Quartus, NIOS II ]
Implemented basic low pass filter using Verilog by Altera Quartus Software and analyzed performance difference due to calculation of multiplication using Altera Megawizard as Hardware Accelerator.
Implementation of low power multiplier circuit using cadence tools. [ Cadence Virtuoso, Assura ] The circuit of low power multiplier was implemented from scratch using CMOS transistor logic and DRC check and LVS verification of the circuit designed was performed.
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