C,C++, Verilog, Python

DEVANSHI PATEL

**rd S *rd St, San Jose, CA ***** C: 510-***-**** <> ac06w7@r.postjobfree.com

LinkedIn URL: https://www.linkedin.com/in/devanshi-patel-95227baa/ OBJECTIVE

Seeking internship/co-op opportunity in the field of Electrical Engineering, Digital VLSI, SoC Design and Verification Engineering

EDUCATION

M.S Degree in Electrical & Electronics Engineering Fall’16 - Present San Jose State University, San Jose, CA

GPA: 3.2/4.0

Related Coursework: Digital System Design and Synthesis, CMOS ASIC Design, Advance Computer Architecture, Linear Systems, Principles of Semiconductor Devices. B.E Degree in Electronics and Telecommunication Engineering July’10 - June’14 Gujarat Technological University, India

GPA: 3.7/4.0

Related Coursework: VLSI technology & Design, Embedded System, Digital Logic Design, Digital Communication, Microprocessor & Interfacing.

TECHNICAL SKILLS

Programming languages: Verilog HDL, C and C++, Embedded C, Python.

EDA Tools: Synopsys VCS, Design Compiler, Design Vision, Keil.

Soft Skills: Self Motivated, Team Player, Effective Communication Skills, Adaptable to work environment, Problem Solver, Quick Learner and good listener. PROJECTS

IFFT using Butterfly Matrix [Verilog HDL] Spring’17

Designed and implemented 32-point IFFT using radix-2 butterfly matrix in Verilog

VCS simulation, Gate level simulation and NC Verilog simulation were performed using Cadence SimVision tool Single Level Cache simulator [C++] Spring’17

Designed single level cache simulator in Verilog HDL

Implemented different cache design parameters like Cache size, Line size, Set size, Cache placement algorithm, Cache replacement algorithm and Write policy

5-stage pipelined Altera Nios- 2 RISC architecture [Verilog HDL] Spring'17

Designed and implemented 5 stage pipelined NIOS-II architecture in Verilog

Each stage of pipeline dedicated for Fetch, Decode, Execute, Data memory and Write back cycle respectively and Supports all R-Type, I-type and J-type instructions ASIC design of log calculator [Verilog HDL, Encounter] Spring’17

Optimized the given design at 250MHz and 333MHz freq with the use of 2-flag push pipeline model

Created Placement and Routing Schematics for the design and eliminated Timing violations 5 Stage Pipelined Floating point adder [Modelsim] Spring’17

Implemented IEEE single precision floating point adder for signed and unsigned numbers

Design was modeled at Verilog RTL code which could perform addition of IEEE 754 standard 32 bit operands

Eliminated arithmetic hazards of IEEE754 addition by implementing 5-stage pipeline 64Bit Signed Binary Multiplier-Divider circuit [Synopsys VCS, DC] Fall’16

Designed FSM-based multiplier-divider circuit in Verilog HDL and modeled at RTL level

ALU implemented using 32 bit CLA and design was synthesized at 125MHz clock

Performed Pre-synthesis (RTL) functional verification and Post-synthesis (Netlist) functional and timing verification using Synopsys VCS simulation tool

Optimized performance of the design by observing clock period, total time delay for an operation

(Multiplication/division), area and power

RESEARCH PROJECTS

“UVM methodology for verification of IC Designs” Spring’17 Supervised by Professor: Dr. James Freeman, Grade: A

Learnt basic UVM concepts

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