Design Engineer

Varun Sharma

*****.******@***.*** +1-347-***-****

** **** ***** ******, *** Jose, California -95125

http:/www.linkedin.com/in/91varunsharma http://www.github.com/91varunsharma New York University, Tandon School of Engineering, Brooklyn, New York May 2017

• MS in Computer Engineering (Graduate Scholarship) Teaching Assistant- New York University (Jan.2016-May.2017)

• To help students develop a digital circuit based game using schematic based design on Xilinx ISE and play it on FPGA board

• The game involves state machine based design to develop a player that would play against professor's player

• Managing & grading the semester long design project of students & help them in Digital logic and State machine concepts Mentor Summer Research Program- New York University (Jun.2016-Aug.2016)

• Supervised research students in developing Reconfigurable software with reconfigurable Hardware on FPGA where we designed a multiplayer game using Verilog HDL on Xilinx Vivado and C++ to develop GUI for communication between FPGA board and PC Guru Gobind Singh Indraprastha University, New Delhi, India June 2013

• Bachelor of Technology (Electronics & Communication) (1st Class with distinction) Digital Design:

• RTL Design and Implementation of Single cycle MIPS processor using VHDL on FPGA (Nov. 2016-Dec. 2016) 32-bit MIPS processor was written in VHDL using Xilinx ISE and ran it on FPGA at 100 MHz clock frequency Implemented complete RC5 encryption & decryption using the MIPS instructions on the processor designed using VHDL.

• Built-In-Self-Test memory design using Verilog (Feb. 2017-Apr. 2017) The BIST structure generate patterns and compares output response for a dedicated piece of circuitry. VLSI :

• Design & Enhancement of On-Chip Optical Interconnect Performance (Feb. 2016-May. 2016) Modelled the VCSEL (Vertical Cavity Surface Emitting Laser) based optical modulator using MATLAB Simulink Comparison of electrical and optical interconnects indicated that latter is better for data transmission in high speed ICs.

• Memory System Design 256-bit (6T- SRAM) & Layout using 45nm technology (Sep. 2015-Dec. 2015) Read & Write margins were 30% and 50%, 6-T SRAM cell layout area < 1μm2, clocking frequency of 1.5 GHz and power supply as low as 780mV were achieved.

Embedded Systems :

• Coaxial Rotor Aerial Vehicle (Jan. 2013-May. 2013) A coaxial rotor Copter was designed using ATMEGA 168PA IC (Arduino) capable of carrying a camera in order to perform Live monitoring of the area.

• Accelerometer Based Gaming Console using ARM based microcontroller (Feb.2016-May. 2016) Developed a standalone gaming device for a multiplayer Artillery Game. Users provide inputs to their players from the on board accelerometer of STM32F4Discovery ARM microcontroller and the game is played on an LCD interfaced with the board. Analog Design :

• Successive Approximation Analog to Digital Converter on 180nm technology node(ADC) (Jun.2016-Aug.2016) Capacitor array DAC was designed to achieve high speed with medium resolution. SAR architecture had in built sample and hold circuit, so there was significant saving of chip area.

• Two Stage Operational Transconductance Amplifier design on 180nm technology node (Apr.2016-May.2016) A two-stage amplifier was designed using 180nm technology on Cadence virtuoso with Phase Margin- 72.8 Degrees, Closed Loop Gain~2, Open Loop Gain-59.1dB, Slew Rate-34.13 V/uS, GBW(0dB)-43.26 MHz, GBW(-3dB)-30.6 MHz.

• Designed low-noise, low-power radiation sensor on 250nm technology node (Feb.2016-Apr.2016) Designed low-noise, low-power Industry level radiation sensor using CMOS 250nm technology at 2.5 V supply voltage. It consisted of sensor, Charge Shape Amplifier and pulse shaper. PROJECTS

EDUCATION

Computer Architecture :

• Design of Multilevel Cache memory simulator using C++ Nov. 2016 Designed a multilevel cache memory system simulator in C++ using round-robin replacement policy on cache accesses

• 32-bit MIPS Processor Simulator using C++ Oct. 2016 Designed an instruction-level simulator for a single cycle MIPS processor in C++ which model the execution of each instruction.

• Branch Prediction Simulator for Hardware Speculative MIPS Processor using C++ Dec. 2016 Simulated branch prediction using 2-bit saturating counter technique which predicts whether the branch is taken or not depending on the state of the saturating counter and update its state accordingly. Programming skills: C, C++, VHDL, Verilog, System Verilog, Embedded C, Assembly language, Perl Designing Tool: Cadence Virtuoso, Hspice, LabVIEW, MATLAB, Xilinx ISE, Vivado, Mentor Graphics ModelSim, Altera Quartus Other Computing skills: Data structures, OS, MS Office Hardware skills: ASIC, FPGA, ARM, VLSI floorplan, STA, Clock tree synthesis (CTS), CDC, Clock gating, Physical design, RTL coding, Cache design, Advance pipelining, Multicore processors, CPU/microarchitecture, SoC, SRAM, Layout design, CMOS, Logic design, P&R, signal integrity, synthesis, timing closure, crosstalk, microcontrollers, DDR3, USB, I2C, SPI, PCIe, Logic analyzer, LVS, DRC Project Fellow- National Physical Lab, India (Nov. 2014-Aug. 2015)

• Did Virtual Instrumentation & Automation using LabVIEW

• Measurements of transport properties (R-T & I-V) of superconducting thin films at low-temperature up to 4 Kelvin Graduate Engineer Trainee - Nokia Solutions & Networks (NSN), Noida, India (Dec.2013-Sept. 2014)

• Solved WCDMA/HSPA/LTE/WiFi queries for leading telecom operators. Customized solution building & Tool based network dimensioning. Defined and documented technical customer solution and responding to technical parts of tenders. Electronics Intern- Solid State Physics Laboratory, India (Feb. 2012- Aug. 2012)

• Characterized Lead based and lead free piezoelectric and pyroelectric materials. Tested their Electrical properties using Probe analyzer, LCR meter.

• Performed Microscopy (SEM) on devices including wafers and ICs.

• Performed Visual Inspection, Electrical analysis, chemical analysis, cross- sectioning of samples (including Polishing),sputtering, working knowledge of doing FIB cuts.

• Anvinder Singh & Varun Sharma (2013) Design analysis and construction of energy harvesting coaxial helicopter, Aviation, 17:4, 145-149– Taylor & Francis

• Anvinder Singh & Varun Sharma (2015) Techno-logical aspects of Time travel, IJAREAS, 4:2, 88-98-GARPH Industry Experience

PUBLICATIONS

TECHNICAL SKILLS

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