Analog, Mixed Signal and High-speed layout

Shrinivas Kulkarni

669-***-****(c) San Jose, CA *5134 ************@*****.***

IC Mask Layout Design Engineer

Extensive experience in analog, mixed signal custom and highspeed IO layout design on chip tape-outs. Responsible for floor planning, block placement, signal routing, power plans & integration process, worked on Cadence Virtuoso 12.1, CCAR, Assura LVS and RCX, and Calibre and Hercules DRC, LVS, ERC, Density, HV, ESD, Latchup, Antenna Excellent communication skills and work well with cross-functional team. Very motivated and willing to quickly learn.

Technical Skills:

Design low noise, and low power analog blocks with tight matching, resistors, capacitors, IO pad, ESD structures, guard ring, etc.

Design of highspeed IO layout with low capacitance in deep sub-micron CMOS process node

Understand issues of Latch-up, IR drop, RC delay and cross capacitance

Special planning during placement targeting density, HV, EMIR, antenna and DRC in deep sub-micron processes like Intel 10nm, 14nm and 22nm

Knowledge of device structures, experience with analog and DFM best practices

Familiar with analog layout techniques such as common centroid and interdigitated matching, shielding, separate power supplies and substrate isolation

Basic layout: bipolar and CMOS transistors, diodes, standard cells and macro cells

Floor plan: Cell/block placement, pad, power bus and signals arrangement

Good understanding of high-speed layout considerations, such as parasitic, crosstalk isolation, supply and bias distribution.

Professional Experience:

AMS Engineer Aricent NA INC San Jose, CA Aug 2016-present

Layout from placement to top level block verification for LDO with density, antenna erc and EMIR clean.

Sr. Lead Engineer Aricent Technologies India Pvt. Ltd. India 2011.5-2016.9

Completed error free complex layout design of Highspeed IO with programmable TX and RX, Layout design was used to present a Technical paper on Low cap Programmable IO

Accomplished layouts of family of LDOs, a very critical project and completed on time without compromising on quality

Layout of RDAC in a challenging area

Layout of Ring Oscillator and HV LDO

Sub Sytem level assembly, ECO fixing

All layout activities completed in Intel 10nm 14nm and 22nm and TI 350um BICMOS process

Member Of Technical Staff, Karmic Design Centre, India 2006.7-2011.5

Accomplished power management Testchip in TSMC 45nm process. With ESD clean and all special current and shielding signals taken care of.

Completed layout of high current LDO along with IO pad and ESD cell.

Layout of SAR ADC with challenging cap array to get ideal step voltages at the output

Layout of AMP for PLL, Bias Generator placement and routing using TSMC 45nm and 65nm CMOS process.

Pad Ring creation for Testchips, cleaning up ESD for the ring in 45nm TSMC process

Physical verification, debug DRC and LVS and fix Antenna and Metal density in chip level.

Education:

BE in Instrumentation Engineering, BVB College OF Engineering and Technology, Hubli, India

Additional Trainings and Certificates:

6 months of rigorous VLSI training at KarMIC Design Centre 2006, targeting Circuit Design and Fabrication Process in detail

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