GAURAV SAHASRABUDHE

Address: *** ***** ******, **** *, Sunnyvale, California, 94087 Phone: +1-312-***-****

Email:ac01a1@r.postjobfree.com

https://www.linkedin.com/in/gauravsahasrabudhe

SUMMARY:

- Technology professional with expertise in Memory Design, Digital Design, frontend VLSI with focus on Hardware Design.

- Strong collaborator with ability to bring technical knowledge and skills in programming, designing to contribute to complex projects.

- Skilled in ASIC Design, Verilog, Computer Architecture, CDC, Static timing analysis, FPGA Design, SPICE, FSM Design, DRC, LVS

- Knowledgeable in System Verilog, Test Benches, Design Verification, Cache Coherence, Snooping Protocols, Microprocessor, ATPG

- Possess hands-on experience with EDA Tools, Scripting and HDL’s gained from academic course projects and work experience.

EDUCATION:

University of Illinois at Chicago 2013 – 2015

Master’s Degree in Electrical and Computer Engineering, 3.61 GPA Chicago, IL

University of Mumbai, V.E.S. Institute of Technology 2008 – 2012

Bachelor’s Degree in Electronics Engineering, 3.7 GPA Mumbai, India

SKILLS:

EDA Tools : QuestaSIM, Cadence-Virtuoso, PSPICE, Altera Quartus 13.0, ModelSIM, Matlab, Atalanta (ATPG)

Programming Languages: C, C++, Verilog, VHDL, HSPICE, Shell Scripting, Perl, System Verilog

Operating Systems and Lab Equipment: Linux, Windows, Oscilloscopes, Multimeter, Function Generator,USB,RS-232, Ethernet

WORK EXPERIENCE:

Independent Contractor (ASIC Design) at Scalable Systems Research Labs Inc. (San Jose, California) (2015-2017)

-Oversaw parser and internal switches that control of flow of data and commands for a Host Adapter.

-Gained experience working with a Host Adapter as part of a Hybrid Memory Cube-based memory ASIC (VlcRAM) and hands-on coding experience using Verilog on Altera Quartus and Xilinx Vivado.

-Designed FSM for controller of HMC Interface and memory management for HMC. Also designed asynchronous FIFO and dual port SRAM to handle issues of CDC for different reads and writes.

-Designed a 39 bit TCAM and its sub-blocks in vlcRAM ASIC which included SRAM/DRAM Read, SRAM Write and DRAM Write FSM. Designed the behavioral model of the CAM and conceptual RTL design of an Ethernet packet processor storing sources address in it.

-Developed experience working with cutting-edge technologies and advances in VLSI, specifically related to memories.

Graduate Assistant at University of Illinois at Chicago (UIC) (2014- 2015)

-The job involved hardware trouble shooting, use of active directories, setting up proxy servers and networking of staff machines.

-Took initiative in setting up/deploying new machines. Trained other new graduate assistants. Resolved 33 % more user requests.

Associate Software Engineer at Accenture Services Private Limited (Mumbai, India) (2013)

-Worked as a Java Developer in coding on Thunderhead software facilitating the client with contract documents. Also learned concepts of AJAX, XML and Servlets

ACADEMIC PROJECTS: (August 2013- May 2015)

Verilog HDL Design And Verification : (Altera Quartus II 13.0):

-Designed and simulated Multiple Interacting FSM’s to determine the modulo-3 of an n bit number. Used one hot coding technique and Divide and Conquer strategy to obtain a constant speed of n/4 cycles. Got lowest delay for FSM 7.692 ns amongst all teams.

-Designed and implemented an adder that adds 3 numbers giving an 18 bit Sum output using wait and design for all cases (DAC) strategies. A detailed analysis of hardware cost vs time along with STA was made. Got above average performance metric.

Cache Replacement Policies and Blocking Matrix Method (C++, Simple Scalar Simulator)

-Implemented MRU cache replacement policy for heap sorting applications. It resulted in 30% higher cache miss rates than LRU

-Used blocking/non-blocking methods for NXN matrix multiplication. Blocking improves execution time due to increased temporal locality

VLSI Schematics and Layouts: ( Cadence Virtuoso and Schematic Editor):

-Designed schematic and Layout of a 4 bit Synchronous ALU based on a 6:1 MUX performing functions like 4 bit addition, 4 bit Addtraction, 4 bit static NAND. Used mirroring technique and XOR-XNOR strategy to design adders to reduce hardware cost by 15%.

-Performed DRC and LVS check, followed by parasitic extraction. Achieved minimum layout area allowable within DRC.

ATPG Based Fault Testing and Simulation: (Atalanta and Hope Simulator)

-Analyzed and compared the k-detectability of Atalanta generated test vector sets with random test vector sets. Data was plotted for a benchmark of combinational circuits ranging for 17-7k gates. Analyzed DFT for sequential circuits using Scan chain and compression.

-Presented lecture on various DFT Methods including AdHoc, full scan and partial scan chain techniques.

Parallelization of Circuit Selection Problem in CAD: (MS Visual Studio)

-Developed an efficient algorithm for solving the Min-Cost-Network-Flow formulation of Circuit Selection Problem using Push-Relabel technique. Parallelization was done and was tested on multicore processors (2, 4, 8) for reduction in execution time.

-A time reduction of 25% was obtained for dynamic load balancing and 75% for static load balancing on 8 cores versus a single core.

CERTIFICATIONS AND TECHNICAL TRAINING:

Achieved an A grade in a certificate course of ‘VLSI DESIGN AND TOOLS’ on Cadence conducted by college. Designed schematics, layouts and calculated worst case propagation delays using DRC rules for logic gates, fast adders and SRAM cells.

VOLUNTEER WORK:

-Served as a committee member for the Indian Graduate Student Association UIC. Provided free of cost temporary accommodation and pickups for 300+ graduate students at UIC. Helped in promoting, bringing sponsorships and arranging cultural events.

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