Logic Design, Digital Design, RTL Design, Verification.

Shivangi Katiyar

San Jose, CA-***** 669-***-**** ac0tbf@r.postjobfree.com www.linkedin.com/in/shivangi-katiyar-a967b654 SUMMARY

Graduate student, seeking an opportunity in the field of Electrical Engineering where my extensive knowledge and skills can be used to readily accept the upcoming challenges offered by the global market and deliver the best services for the growth of the industry. EDUCATION

Master of Science in Electrical Engineering Aug 2015 – May 2017 San Jose State University, CA

Advanced Coursework: Digital System Design & Synthesis, ASIC CMOS Design, Advanced Computer Architecture, SOC Design/Verification, RFIC Design I, Special Topic in Digital Design (UVM). Bachelor of Technology in Electronics and Instrumentation Engineering Aug 2009 - July 2013 Visvesvaraya Technological University (VTU), Bangalore, India TOOLS AND TECHNICAL SKILLS

Skills: Digital Design, Logic Design, RTL Coding, ASIC Design Flow, SoC Design, Simulation, Synthesis, Static Timing Analysis (STA), Dynamic Timing Analysis (DTA), Time Fixing, Debug, DFT SCAN, Verification, Test Case Generation, Test Plan Development, VIP Development, Assertions, Coverage, OOPs, Functional Verification, Coverage Driven Verification, Computer Architecture, Pipelining. Programming Languages: Verilog, SystemVerilog, UVM, Python, C. Protocols: I2C, SPI, AMBA APB, AHB, AXI, NoC.

CAD Tools: Synopsys VCS, Synopsys Design Compiler, GTKWave, Altera Quartus, Xilinx Vivado, Cadence Virtuoso

ACADEMIC AND RESEARCH PROJECTS

Network on Chip Bus using SoC Architecture and Network Topology [System Verilog, UVM] May 2017

Implemented a three-level network topology serial bus using router. The router would route the data to and from the sixty-four devices using device address mechanism. The router had 18-bit interface, 9-bit coming in & 9-bit going out of router. The design was made to synthesize at 100 MHz and functionality of bus was verified using UVM methodology. Network on Chip Bus [System Verilog, UVM] Feb 2017

Implemented a Network on Chip bus that would communicate with the devices connected onto it using different types of packets. The bus supports burst up to 128 bytes and it is a fully split bus. The bus was made to synthesize at the clock frequency of 100 MHz using Toshiba Technology Library. Developed a detailed test plan to verify the functionality of the bus. Created the UVM framework, containing Sequence, Sequencer, Driver, Agent, Monitor, and Scoreboard. Sequences were created that would check the bursts up to 128 bytes and split functionality of the bus. Performed Code Coverage and Functional Coverage. Cyclic Redundancy Check [System Verilog, Synopsys VCS, UVM 1.2] Sep 2016

Designed, Synthesized and Verified CRC 16/32- bit protocol. The designed was made to run at the clock frequency of 100 MHz using Toshiba 240 library.

Gaussian Noise Generator using Box-Muller Method [Verilog, Toshiba 0.18um, Synopsys VCS] Apr 2016

Implemented and Synthesized the Box-Muller transform to convert two random numbers to an approximation of Gaussian random number distribution in Verilog. The design was made to run at 220 MHz clock frequency. Implemented DFT functionality using SCAN Chain. Performed STA and fixed long path issue by incorporating pipelines in the design. NIOS II Processor ALTERA (MIPS Processor) [Verilog, Synopsys VCS] Mar 2016

Implemented NIOS II architecture in Verilog using five-stage pipelined with data forward chaining algorithm in Altera Quartus II and simulate the code using dot product and factorial as a benchmark program. Developed a Test Plan to completely verify the functionality of Instructions. Performed Code Coverage and Functional Coverage for defined Cover points. Floating Point Adder and Multiplier [Verilog, Toshiba 0.18um, Synopsys VCS] Dec 2015

Designed double precision floating point adder & multiplier. Increased the clock frequency of design from 100 MHz to 300 MHz using two flag push model pipelining. Generated Clock Tree and performed Place & Route using Encounter. WORK EXPERIENCE

Himalayan Institute of Technology and Management, India Assistant Professor Feb 2014 - Feb 2015

Assistant Professor in Electronics and Communication department.

Conducted classes on Digital Design and Basic Electronics.

Included labs and department research work.

RECOMMENDATION

Available on request.

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