| Resume alert | Resumes 141 - 150 of 450 |
VLSI Digital Design Engineer
Santa Clara, CA
... VHDL/Verilog Design, Implementation and Synthesis on both Altera and Xilinx Platform. Verilog synthesis, placement and routing and debugging using Synopsys VCS and analysis using design vision. WORK EXPERIENCE: COTMAC ELECTRONICS PVT.LTD. - Intern ... - 2017 Jul 03
... VHDL/Verilog Design, Implementation and Synthesis on both Altera and Xilinx Platform. Verilog synthesis, placement and routing and debugging using Synopsys VCS and analysis using design vision. WORK EXPERIENCE: COTMAC ELECTRONICS PVT.LTD. - Intern ... - 2017 Jul 03
Design Engineer
San Jose, CA
... in developing Reconfigurable software with reconfigurable Hardware on FPGA where we designed a multiplayer game using Verilog HDL on Xilinx Vivado and C++ to develop GUI for communication between FPGA board and PC Guru Gobind Singh Indraprastha ... - 2017 Jul 03
... in developing Reconfigurable software with reconfigurable Hardware on FPGA where we designed a multiplayer game using Verilog HDL on Xilinx Vivado and C++ to develop GUI for communication between FPGA board and PC Guru Gobind Singh Indraprastha ... - 2017 Jul 03
Design Engineer Electrical Engineering
Mountain View, CA, 94040
... Implemented following FPGA blocks using Verilog: A controller block that utilize I2C and SPI master controllers to communicate with multiple MEMS gyros and accelerometers. The user could change communication protocol, clock speed, frame size and ... - 2017 Jun 28
... Implemented following FPGA blocks using Verilog: A controller block that utilize I2C and SPI master controllers to communicate with multiple MEMS gyros and accelerometers. The user could change communication protocol, clock speed, frame size and ... - 2017 Jun 28
ASIC Design Engineer
Sunnyvale, CA
... - Skilled in ASIC Design, Verilog, Computer Architecture, CDC, Static timing analysis, FPGA Design, SPICE, FSM Design, DRC, LVS - Knowledgeable in System Verilog, Test Benches, Design Verification, Cache Coherence, Snooping Protocols, Microprocessor ... - 2017 Jun 27
... - Skilled in ASIC Design, Verilog, Computer Architecture, CDC, Static timing analysis, FPGA Design, SPICE, FSM Design, DRC, LVS - Knowledgeable in System Verilog, Test Benches, Design Verification, Cache Coherence, Snooping Protocols, Microprocessor ... - 2017 Jun 27
Digital/Hardware Engineer
Fremont, CA, 94537
... Programming Language: C, C++, Java, Embedded C, VHDL, Verilog, Arduino and Python. Microprocessors & Microcontrollers: Intel 8085, 8086, ARM7, Intel MCS-51, 80C51, Raspberry Pi, Arduino, Atmega 8, 16, 24, PIC, MSP430 Protocols: USB, CAN, SPI, I2C, ... - 2017 Jun 24
... Programming Language: C, C++, Java, Embedded C, VHDL, Verilog, Arduino and Python. Microprocessors & Microcontrollers: Intel 8085, 8086, ARM7, Intel MCS-51, 80C51, Raspberry Pi, Arduino, Atmega 8, 16, 24, PIC, MSP430 Protocols: USB, CAN, SPI, I2C, ... - 2017 Jun 24
Logic Design, Digital Design, RTL Design, Verification.
San Jose, CA
... Programming Languages: Verilog, SystemVerilog, UVM, Python, C. Protocols: I2C, SPI, AMBA APB, AHB, AXI, NoC. CAD Tools: Synopsys VCS, Synopsys Design Compiler, GTKWave, Altera Quartus, Xilinx Vivado, Cadence Virtuoso ACADEMIC AND RESEARCH PROJECTS ... - 2017 Jun 12
... Programming Languages: Verilog, SystemVerilog, UVM, Python, C. Protocols: I2C, SPI, AMBA APB, AHB, AXI, NoC. CAD Tools: Synopsys VCS, Synopsys Design Compiler, GTKWave, Altera Quartus, Xilinx Vivado, Cadence Virtuoso ACADEMIC AND RESEARCH PROJECTS ... - 2017 Jun 12
Engineer Design
San Jose, CA
... Eight years of experience in Front- end hardware RTL design, simulation, synthesis, timing analysis, verification using Verilog, VHDL,C/C++,Perl,Tcl/TK for ASIC/FPGA. Designed RTL for CPU-GPU processor, DSP Processor, ARM Processor, MPEG chip, CDMA ... - 2017 Jun 10
... Eight years of experience in Front- end hardware RTL design, simulation, synthesis, timing analysis, verification using Verilog, VHDL,C/C++,Perl,Tcl/TK for ASIC/FPGA. Designed RTL for CPU-GPU processor, DSP Processor, ARM Processor, MPEG chip, CDMA ... - 2017 Jun 10
Design Electrical Engineering
Santa Clara, CA
... Smart ACE, Design Vision, Prime Time, IC Compiler, Library Compiler, Wave View), Multisim, Keil, TetraMax Hardware Languages Verilog, System Verilog Programming Languages C, Java, MATLAB, Python, Perl Operating Systems Windows, Linux Hands on ... - 2017 Jun 06
... Smart ACE, Design Vision, Prime Time, IC Compiler, Library Compiler, Wave View), Multisim, Keil, TetraMax Hardware Languages Verilog, System Verilog Programming Languages C, Java, MATLAB, Python, Perl Operating Systems Windows, Linux Hands on ... - 2017 Jun 06
Design and Verification Engineer
San Jose, CA
... Languages: System Verilog, UVM (Basic), Verilog HDL, VHDL, PERL, C programming. Applied Skills: AXI VIP, OOP, Coverage, Assertions, Pipelining, Gate level synthesis, Instruction level parallelism, STA, EDA tools, Constraint Randomization. Tools: ... - 2017 Jun 05
... Languages: System Verilog, UVM (Basic), Verilog HDL, VHDL, PERL, C programming. Applied Skills: AXI VIP, OOP, Coverage, Assertions, Pipelining, Gate level synthesis, Instruction level parallelism, STA, EDA tools, Constraint Randomization. Tools: ... - 2017 Jun 05
Information Security Engineering
San Jose, CA
... Skills Design Tools Cadence, Synopsys, LabVIEW Microprocessors Arduino, Altera DE0 Nano (Cyclone IV) Programming Tools VHDL, Verilog, System Verilog, Matlab Operating Systems Windows, Mac, Linux Information Security NeXpose, Fortify, DarkTrace, ... - 2017 Jun 05
... Skills Design Tools Cadence, Synopsys, LabVIEW Microprocessors Arduino, Altera DE0 Nano (Cyclone IV) Programming Tools VHDL, Verilog, System Verilog, Matlab Operating Systems Windows, Mac, Linux Information Security NeXpose, Fortify, DarkTrace, ... - 2017 Jun 05