Information Security Engineering

Abhilash Nagaraj +1-937-***-**** ac0o0q@r.postjobfree.com

Address: **** ***** ***, ****** *****, California 94598 LinkedIn: https://www.linkedin.com/in/abhilash-b-n-bb4867105 Objective

To secure a full-time position in the field of Electrical and Electronics Engineering allowing me to use my technical skills and abilities towards the growth of the organization while gaining valuable experience Education

Master of Science in Electrical Engineering - May 2017 Wright State University, Dayton, Ohio, USA

GPA – 3.9/4

Bachelor of Engineering in Telecommunication Engineering - July 2015 Visvesvaraya Technological University, Belgaum, Karnataka, India GPA – 3.5/4

Related Coursework

VLSI Circuit Design

VLSI Design Synthesis and optimization

Low Power VLSI System Design

Digital IC Design with PLD’s and FPGA’s

Embedded Systems

Advanced Communication Networks

Fundamentals of EE

Mixed Signal Processing

THz Electronics

Technical Skills

Design Tools Cadence, Synopsys, LabVIEW Microprocessors Arduino, Altera DE0 Nano (Cyclone IV) Programming Tools VHDL, Verilog, System Verilog, Matlab Operating Systems Windows, Mac, Linux Information Security NeXpose, Fortify, DarkTrace, LogRhythm Others C, C++, Python, Perl, OVM/UVM Work Experience

Blackhawk Network, Pleasanton, California, USA June 2016 – August 2016 Role – Information Security Intern

Worked on Rapid 7 NeXpose Vulnerability Management tool and HPE Fortify Static Code Analysis tool to resolve tickets

Assisted in data recovery and then took lead on E-Forensics project. Helped in creating network policies using PAN

Operated on DarkTrace, PAN, SEP, vSphere client and RedSeal to resolve any issues and to keep the entire network protected

Researched Key Exchange, EMV, SIEM, Patch Management and Network protocols Academic Projects

Floorplanning, Placement and Delay Optimization using PERL May 2017

Conducted a comparative study of Automated & Manual approach towards EDI systems to study design flows for different ckts

Coded in VHDL and synthesized the test ckts to arrive at schematics and layouts, ran automated design flow to get PDA values

Wrote PERL script and synthesized test ckts to get schematics & layouts, created manual FP & Placement to get 23% better PDA Low Power Sequential Circuit May 2017

Was exposed to System Verilog and UVM technologies to run testbenches to study functionalities and timing analysis (STA)

Altered codes, ran different test cases to study variations in timing and skews to isolate False paths and ways to overcome it 6X6 Booth Multiplier March 2017

Implemented a booth multiplier which generates output with 60% more speed. Produced the logic for ENC, MUX & Logic Shifters

The adder circuits were developed using the circuit of 24 transistor mirror adder with inversion property to reduce area & delay

For the above designs, structured the schematics and layouts in Cadence and optimized it to extract the least PDA. Calibration of Accelerometer December 2016

The objective was to control the accelerometer to obtain its values 25% before excitation and 75% after excitation

Integrated Altera DE0 Nano (inbuilt accelerometer) and Arduino Uno with Visual Studio (also Matlab) to output values graphically 4-Bit ALU April 2016

The goal was to design an ALU to perform logic operations as A, A’, A&B, A B and Arithmetic operations as A++, A--, A+B, A-B

Designed the schematics and layouts in Synopsys for all basic gates (2 & 3 input), DFF, 1-bit & 4-bit adder; using these, schematics and layouts for 4-bit ALU were designed to realize the objective. They were optimized for high speed and to yield the least PDA 16 Point FFT I - April 2016, II - December 2016

I - Designed the structure to feed 10-bit input from an 8-bit sine wave generator, designed FFT block to perform computations, wrote logic for maximum bin detector and displayed output in 10 bits using LCD control on a Xilinx Vertex6 Board using VHDL

II - Used Cadence encounter tool to generate RTL circuits and Layouts for the FFT code and optimized it to get the best PDA LabVIEW GUI Based Air Cushion Vehicle – Hovercraft May 2015

Built the body of hovercraft to withstand harsh conditions; constructed the front panel and block diagram of GUI in LabVIEW

Integrated microcontroller with Ultrasonic Range Finders, Temperature sensors and a Wireless camera to monitor surroundings

The designed prototype of unmanned hovercraft fit perfectly for domestic applications; provided remote access using Zigbee Certifications

Core 1 and Core 2 training in LabVIEW (Oct-2013)

Vocational training on Comm. Networks at BSNL (July-2013)

Dynamic skills integrated program certified by CIL(Sept-2014) Publication – “LabVIEW GUI Based Air Cushion Vehicle – Hovercraft” May 2015

LabVIEW GUI Based Air Cushion Vehicle – Hovercraft. IJERT International Journal of Engineering Research and, Volume. 4, May

– 2015 (Issue. 05) http://dx.doi.org/10.17577/IJERTV4IS050677

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