Design Electrical Engineering

SUPREET SHIVANAND KHANAPET

Phone : +1-469-***-****, Email: ac0pur@r.postjobfree.com

**** ******* ***, *** *, Santa Clara, California - 95051

https://www.linkedin.com/in/supreet-shivanand-khanapet-7a311475 OBJECTIVE: Seeking full time opportunity in the field of ASIC/VLSI/Logic/Physical/RTL Design, DFT. EDUCATION

Master of Science in Electrical Engineering GPA: 3.37 University of Texas at Dallas, Richardson, TX, USA Expected Graduation: May 2017 Bachelor of Technology in Electronics and Communication Aggregate: 84.9% Jawaharlal Nehru Technological University, Hyderabad, India June 2015 TECHNICAL SKILLS

EDA Tools Cadence Tools (Virtuoso, Encounter, Spectre), Synopsys Tools(Silicon Smart ACE, Design Vision, Prime Time, IC Compiler, Library Compiler, Wave View), Multisim, Keil, TetraMax

Hardware Languages Verilog, System Verilog

Programming Languages C, Java, MATLAB, Python, Perl Operating Systems Windows, Linux

Hands on Experience with Vector Network Analyzer, Spectrum Analyzer, Digital Storage Oscilloscope, Power Meter, Signal Generator, Multimeter

Pursuing online course at Udemy–SOC Verification using System Verilog ACADEMIC PROJECTS

ASIC Design of Low Power Mini Stereo Digital Audio Processor (Verilog, ModelSim, IC Complier, Design Compiler)

Designed an ASIC chip to implement Digital FIR filter capable of performing audio processing functions

RTL codes written in Verilog and final gate-level netlist was obtained using Design Compiler

Automatic placement and routing is done using IC compiler. Two designs with different placements were designed and better design (w.r.t power & area) is chosen

Power and timing analysis was done using Design Compiler Design and Layout of 8T SRAM Memory Array (Manual Placing and Routing, Static Timing Analysis, DRC, LVS)

Designed a 256-word Memory array of 8T static memory cells

The decoders, pre-charger, write driver, clock buffer and sense amplifier were sized and designed taking into consideration the load capacitances and logical efforts of the paths

The final placement and layout was done manually in Cadence with minimum total area

HSPICE/SPECTRE was used to check the functionality along with measuring the worst case read and write times of the memory

Design and Implementation of a 64 bit Arithmetic Unit (Verilog, LINUX, CAD Tools, Cadence Encounter)

Designed and implemented an Arithmetic Unit performing 64 bit arithmetic operations using Xilinx ISE and Verilog HDL; DRC, LVS, & QRC was done using Cadence Virtuoso and Composite Schematic

Cadence Encounter was used for floor planning, placing and routing of the implementation

STA is performed using Synopsys PrimeTime. Power & area report is generated using Design Vision Fault Detection, Simulation and Sampling of implemented Combinational Circuits (TetraMax, ATPG)

Implemented combinational circuits at gate level using Verilog & Xilinx ISE and race conditions were avoided

Detected stuck-at-faults (Collapsed and Un-collapsed) and were eliminated, test vectors and the fault coverage was found using Tetramax tool

Demonstrated fault simulation using Parallel, Deductive, Concurrent fault simulation and Critical path tracing methods

Test pattern is generated for Built-In self-test(BIST), Boundary Scan and different scans are dealt Design and Implementation of High Performance Arithmetic and Logic Unit (MTCMOS, Cadence Virtuoso)

Cadence based design of ALU to compute 8-bit Arithmetic & Logical operations using a 4X1 MUX and a full adder

This project was implemented for minimal power & board area without compromising speed

MTCMOS technology was used for optimizing power & is calculated using Virtuoso - Analog Design Environment Cache Optimization (Gem5, Python)

Cache hierarchy was fine-tuned on X86 architecture based on the gem5 simulator

The cache design parameters which were modified for optimization are Cache levels, cache size, replacement policy, associativity and block size hence changing the Cycles per Instruction

These configurations were experimented on 5 different benchmarks namely 401.bzip2, 429.mcf, 456.hmmer, 458.sjeng and 470.lbm. The tradeoff considered was cost vs CPI ACADEMIC ACHIEVEMENTS

• Honored with a merit Certificate for National Level paper presentation for “Heliodisplay”.

• Awarded for Detect n Design event at IEEE Tech Fest 2013 held in Hyderabad, in which flaws in various circuits had to be detected and rectified to achieve proper functionality

• Awarded first prize in Robotics events held in CVR College of Engineering as a part of CIENCIA 2K14

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