Engineer Design

Uttam K Bhattacharya, PhD

Phone no: 480-***-****

Email : ********@*****.***

***, ******** ***, **** ****, CA 94015

OBJECTIVE: ASIC/FPGA Design Engineer Back-end(Physical Design) and Front-end.

EDUCATION : i) Completed PhD work from department of Computer Science and Engineering, Indian

Institute of Technology, Kharagpur, WB. India.

ii) MS from the department of Electronics and Telecommunication Engineering, Jadavpur

University. W.B. India.

SKILL/ SUMMARY:

Over a decade of industrial experience with hardware design and software development for ASIC/FPGA base designs.

Taped out more than fifteen (15) multi-million gate, high frequency, low-power chips using Synopsys, Cadence,Magma, MentorGraphic tool sets. World wide people are using some of these designs and couple of these productions are ready to be released for the market.

Industrial Silicon(SOC) tape out experience of ASIC designs for both block level and full chip level Timing closure and Integration for multi-million ASIC design.

More than eight years of experience in ASIC Back- end in Synthesis, insert scan chain for DFT/JTAG, static timing analysis(STA), power planning, floor-planning, place & route, clock tree synthesis(CTS), timing closure, SI analysis, LVS/DRC/Antenna clean & verification, Power analysis and correlation with other sign off tools.

Super low power implementation methodology staring from proper RTL coding, Synthesis, clock gating, power gating, specifying proper UPF/CPF, using Multi-VT cells, creating Multi-Voltage domain, Floorplanning, Power Planning, messaging the synthesized Netlist, Managing the P&R for ultimate design closure for making the design to present in the market in time.

Eight years of experience in Front- end hardware RTL design, simulation, synthesis, timing analysis, verification using Verilog, VHDL,C/C++,Perl,Tcl/TK for ASIC/FPGA. Designed RTL for CPU-GPU processor, DSP Processor, ARM Processor, MPEG chip, CDMA/UMTS Technology, Low Power, Wireless Networking, USB, Crossbar Switch,FIR filter,FFT,ROM,RAM,FIFO,Ethernet,TCP/IP, DDR, PCI Express, Fiber Channel.

Customized solution for Timing closure for high performance low power design hand held devices.

Special methodology for resolving Signal Integrity like, Crosstalk and IR-Drop for a world wide used popular processor.

Worked five years on Lattice FPGA tool for both Software and Hardware design and development. Studied and delivered Xilinx and Altera flow for architecture evaluation, benchmarking for Lattice tool in comparison to competitors tools, like Xilinx and Altera.

Supervised and Managed Design group in Lattice Semiconductor and ASIC Design group in TI, Dallas.

More than five years work experience in C/C++ designing, developing, debugging using CVS, RCS and Clear Case.

TOOLS EXPERTISE:

Synopsys : Design Compiler, ICC and ICC2, Physical Compiler, PrimeTime, PT-SI, Test compiler (DFT), Hercules. Familiar with IC Validator.

Cadence : RTL Compiler,Genus, Innovus, EDI Flow, Encounter Timing System(Tempus), Nanorouter,

Conformal/(LEC), NC Verilog.

Mentor : Calibre, Fast Scan, ModelSim/QuestaSim.

Magma : TALUS, Blast RTL, Blast Fusion, Blast Plan, Blast Rail, Blast Noise, Blast Pro.

FPGA : Xilinx Foundation series for VirtexE, Altera FPGA(Max Plus) tool and Lattice tool sets.

Others : Apache RedHawk, UPF, CPF, SpyGlass is for CDC and Lint checking, SystemVerilog, Debussy,

Verdi, Siloti for netlist debugging.

Key words: ASIC, FPGA, Lint, Synopsys, DC, ICC/ICC2, PT, PT_SI, ICV, Cadence, EDI flow, Encounter, Nanorouter, Tempus, Voltas, PVS, RTL2GDS, Place and Route, DFT, AMS, Tcl, UPF, CPF, Physical Design, Verilog, RedHawk.

PROFESSIONAL EXPERIENCE:

Perform the following tasks such as writing Design and Development, RTL coding/fixing, Simulation, Sythesis, Lint checking, Clock Domain Crossing(CDC) Analysis, Scan insertion for DFT, Formal Verification, Floorplanning, Power Planning, Place & Route, LVS/DRC/Antenna clean, final sign-off using for Static Timing Analysis(STA), Power Analysis, Integration for Cluster level & Toplevel and also resolving SI issues for the following companies listed below.

ASIC Design Contractor Engineer at Intel Corporation, Santa Clara, CA, 5G project for external customer support using Intel processor based Ultra High speed(650Mz for GPU) and Super Low power consumer electronics device. The design is for LG’s new electronics device which is consists of more than 25 million gate design targeted for 10m technology using Intel library which consists of nine layers of metal. Responsible for three critical blocks with large no. of hard macros in one of the design, RTL fixing, Synthesis(using Synopsys DC), Constraint writing, Formal Verification(Cadence Conformal) for Low Power, CPF,UPF, DFT, restricted and efficient multi-voltage(4-voltage domain) floor-plan methods to reduce the Congestion, to obtain the best Area, Timing and Power. Used ICC/ICC2 and Innovus for Place and Route, Clock Trees Synthesis, with latest clock tree Synthesis technique to reduce the Skew and Timing failure, LVS/DRC, Antenna Clean, Synopsys Prime Time(PT) for Timing Closure, PT_SI for Crosstalk Analysis, Mentor Graphic Caliber for LVS/DRC/Antenna clean Sign Off, different types of metal fill and RedHawk for IR-Drop Analysis. Responsible for block level full chip integration and design closure. Flow automation using Tcl, Perl. Aug’2016 – Till date

ASIC Design Engineer at Aeroflex Design, Colorado Springs, CO for Low Power Radiation Hard Processor development for Satellites using ARM processor with AMBA protocol for AHB/APB interface in Master Slave configuration . Responsible for RTL bug fixing, Synthesis using Synopsys Design Compiler, Constraints development, UPF, Formal Verification using Cadence Conformal(LEC), Static Timing Analysis(STA) using Synopsys PrimeTime P&R using IC Compiler (ICC) for 28nm node, FinFET TSMC Technology . Flow automation using Tcl, Perl. Feb’2015- Jun’2016

ASIC Design Service Engineer at Cadence Design Systems,Cary, NC of IP development for Low power Mobile Computing with MIPI interface for PCI Express using Cadence (EDI) tool sets. The purpose of this AMS design is to double the frequency of the existing frequencies. It is a 14nm/16nm FinFET technology for nine layer metal with TSMC library. Responsible for more than one design from RTL debugging, Synthesis( Cadence Encounter/RTL Compiler ), Constraint fixing(SDC), CPF, Formal Verification (Cadence Conformal), Formal Verification for Low Power, multi voltage floorplan to obtain the best Timing and Low Power, Place and Route (Cadence Nanorouter), Clock Trees Synthesis(CCOpt), using Cadence ETS for Timing Closure(Tempus), and Sign off, Cadence PVS for LVS/DRC/Antenna clean Sign Off and Cadence Voltas for IR-Drop Analysis. Member for block level and full chip integration and design closure team. Flow automation using Tcl, Perl. Jan’2014 –Jan’2015

ASIC Design Contractor Engineer at Intel Corporation, Santa Clara, CA for dual (Atom) Processor based Ultra High speed(650Mz for GPU), Parallel and Low power Mobile Computing with MIPI interface for Graphic Processor(CPU-GPU). The design is for Intel’s new Smart phone which is consists of more than 30 million gate design targeted for 14nm, high-K,Tri-gate technology library for nine layers of metal. Responsible for two critical clock control blocks with 57 large hard macros in one of the design, from RTL debugging(VCS), Synthesis(DC), constraint fixing, Formal Verification(Conformal), Formal Verification for Low Power, UPF, DFT, restricted and efficient multi-voltage(3-voltage domain) floorplan methods to reduce the Congestion, to obtain the best Timing and Low Power, Place and Route(ICC), Clock Trees Synthesis, with special clock tree balancing technique to reduce the Skew and Timing failure, LVS/DRC, Antenna Clean, Synopsys Prime Time(PT) for Timing Closure, PT_SI for Crosstalk Analysis, Caliber for LVS/DRC/Antenna clean Sign Off and RedHawk for IR-Drop Analysis. Also responsible to full chip Timing Closure and Power Analysis. Responsible for full chip integration and design closure. Flow automation using Tcl, Perl. Jan’2013-Dec.2013

ASIC Design Contractor Engineer at Toshiba Corporation, San Jose, CA for MIPI base Mobile Processor chip for cell phone booster, the design consists of more than 6 million gate design with both analog and digital IP’s targeted for 45nm technology library for nine layers of metal.

Responsible for regular Lint Checking, (SpyGlass), Clock Domain Crossing Analysis, Synthesis(DC), Constraint fixing, Place and Route(Talus), CTS, LVS/DRC/Antenna clean, Synopsys PT for Static Timing Analysis and PT_SI for Crosstalk, Caliber for LVS/DRC/Antenna Signoff . Flow automation using Tcl, Perl. May’2012-Dec.2012

ASIC Design Contractor Engineer at Intel Corporation, Chandler, AZ for Atom based High speed(550Mz) Parallel and Mobile Computing Graphic Processor(GPU) project, more than 12 million gate design targeted for 22nm technology library for nine layers of metal. The design is for new Intel’s Tablet product. Was responsible for two large blocks for fixing RTL bugs, Synthesis (DC), Constraint fixing, Place and Route(ICC), Clock Trees Synthesis, LVS/DRC/Antenna Clean, Prime Time(PT), PT_Si for Crosstalk Analysis, Formal Verification(Conformal), Caliber for LVS/DRC/Antenna clean and Sign Off . Partial responsible for full chip integration and design closure. Jan’2011-April’2012.

ASIC Design Contractor Engineer at LSI Corporation, Mendota Heights, MN for High speed ARM base Mobile Computing Processor project, more than 5 million gate design targeted for 45nm technology library for nine layers of metal. Fixing RTL(NC-Verilog), Constraints, Place and Route (Talus), Clock Tree Synthesis, LVS/DRC/Antenna clean, Synopsys Prime Time(PT) Static Timing Analysis for Timing closure, PT_SI for Crosstalk analysis. Aug'2009-Dec’2010.

ASIC Design Contractor Engineer at Freescale Semiconductor Corporation, Chandler, AZ for High speed Networking Communication project, more than 1 million gate design targeted for 45nm technology library for nine layers of metal. Writing RTL, Synthesis(DC), Constraint fixing, P&R(Encounter), Static Timing Analysis(Encounter CTS), LVS/DRC/Antenna clean, PT_Si for Crosstalk, Voltage Storm for Power Analysis July'2008-June’2009.

ASIC Design Engineer at Intel Corp., Hillsboro, OR for CPU-GPU (Graphic Processing Unit) Processor project 45 million gate design targeted for 45nm technology library for nine layers of metal. This the one of the first Pentium-IV base CPU-GPU design from Intel’s for Xbox. Responsible for three very large blocks with more than 300 different hard macro. Responsible for RTL debugging(VCS), Synthesis(DC), constraint fixing, Place and Route(ICC), Clock Trees Synthesis, LVS/DRC, Antenna Clean, Prime Time(PT) for Timing Closure, PT_Si for Crosstalk Analysis, Formal Verification(Conformal), Caliber for LVS/DRC/Antenna clean Sign Off and RedHawk for IR-Drop Analysis. January 2007-July 2008.

ASIC Contractor Engineer at Qualcomm Corp., San Diego, CA for CDMA-Technology using High-frequency, Low Power and Wireless Chips 9 million gate design targeted for 65nm technology library for 7 layers of metal. The design was the first Qualcomm’s dual modem (consists of both CDMA and UMTS technology) dual ARM Processor(ARM9 and ARM11) for cell phone chips. Responsible for regular Lint Checking, (SpyGlass) Clock Domain Crossing Analysis, Synthesis(DC), Constraint fixing, Place and Route(Talus), CTS, LVS/DRC/Antenna clean Static Timing Analysis(PT). Oct. 2005- Dec. 2006.

Magma Physical Design Contractor at CISCO-Specular Networks, CA, for High speed Networking project targeted for 5 million gate design targeted for 90nm technology library for 7 layers of metal. Responsible for Place and Route(Talus), CTS, LVS/DRC/Antenna clean Static Timing Analysis(PT). . May 2005- Sept. 2005.

ASIC Contractor Engineer at Intel Corp., Chandler, AZ for 4 million gate design targeted for 90nm technology library for seven layers of metal from for PCI-Express design. Writing RTL, Constraints fixing, Place and Route (Apollo Astro), Clock Tree Synthesis, LVS/DRC/Antenna clean, Static Timing Analysis (PT) for Timing closure Oct. 2004 –Apr. 2005.

Magma Physical Design Contractor at Texas Instruments, Dallas, TX for Low power, Wireless Networking Chip based on UMTS Technologies targeted for 5 million gate design targeted for 90nm technology library for 7 layers of metal. Mar.2004-Sept. 2004

ASIC Contractor Engineer at Intel Corp., Hillsboro, OR, for PCI-Express Centrino design project 6 million gate design targeted for 130nm technology library for 7 layers of metal. Writing RTL (VCS), Constraints fixing, Gate Level Simulation. Nov. 2003 – Mar. 2004.

Magma Physical Design Engineer at Magma Design Corp., CA for supporting companies below

i) ST Micro, from RTL to GDSII RAPIDIO, USB, Network file server, 250k to nearly

1 million gate designs, respectively, targeted for 130nm technology, five layers of metal.

ii) WIS Technology, San Jose. project. for MPEG Image processing chip, for 130nm technology,

five layers of metal.

iii) CISCO-TI, San Jose, USA for Giga-bit ethernet router which consists 1.2 GHz, more than

15 million gate design targeted for TI’s 90nm technology library for seven layers of metal.

Aug.2002 – Oct. 2003

Design Engineer at Lattice Semiconductor Corp., San Jose, CA

Benchmark Lattice FPGA with Xilinx FPGA and Altera. Wrote RTL Code, test bench, simulation

and synthesis for designs, including USB, Crossbar switch, FFT, ALU, FIR Filter, UART, core for

DSP processor, PowerPC etc., and for customer designs from field for benchmarking. Software

Design and Development for pin locking and IO Placement for Lattcie FPGA tool by using C/C++

language. Team lead to supervised five engineers for their day to day activity July ‘98 - Aug ‘02

Status : US citizen

SHORT LIST OF TECHNICAL PUBLICATION:

“Isomorphic redundancy for sequential circuits”, IEEE Trans. On Computers, pp 127-132, Sept. 2000.

“A PLA based synthesis scheme for hazard-free realization of circuits”, Proc. 8th. IEEE Intl. Conf. on VLSI Design, pp. 121 to 124, Jan. 1995, New Delhi, India

“Instrumentation for In-Situ monitoring of water quality parameters”, IEEE Transactions on Instrumentation and Measurements, vol 38, no. 3, pp. 820-823, June, 1989.

“Isomorphic redundancy in non-scan sequential circuits". 14th IEEE VLSI Test Symposium, April, 1996, Princeton, USA

“A parallel fault simulation on multiprocessor”, International Journal of System Science, UK, Vol. 23, No. 11, pp. 2025-2035

“A layout driven test generation for CMOS combinational circuits”, IEEE Tencon-94, Singapore, Aug. 94, pp. 823 - 827.

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