Design and Verification Engineer

VIKRAM P. MOHITE

*** ******* ** *** *** Cell: 408-***-****

San Jose, CA-95134 Email: ac0o02@r.postjobfree.com

LinkedIn profile: https://www.linkedin.com/in/vikrammohite

SUMMARY:

2+ years of experience in Digital Design and Verification of various projects with UNIX/LINUX & MS Windows OS.

Experience in handling industry projects and working as a team player with excellent written and oral communication skills.

Interested in Job openings like RTL Design/ ASIC Design and Verification/ Product Development/ Application or Test Engg.

EDUCATION:

Master’s in Electrical Engineering (San Jose State University, CA) GPA 3.31 Bachelor’s in Electrical and Power Engineering (RTM Nagpur University, India) GPA 3.50

TECHNICAL SKILLS:

Skills: ASIC, CMOS, RTL Design, Synthesis, Testing, Verification & Validation, AXI Bus Protocol, SPI Protocol, Computer Architecture, Static Timing Analysis (STA).

Languages: System Verilog, UVM (Basic), Verilog HDL, VHDL, PERL, C programming.

Applied Skills: AXI VIP, OOP, Coverage, Assertions, Pipelining, Gate level synthesis, Instruction level parallelism, STA, EDA tools, Constraint Randomization.

Tools: Questa Sim, Synopsys VCS, MODELSIM, XILINX ISE, Altera Quartus II, MATLAB, Icarus Verilog, NC Verilog,

Cadence Encounter, Cadence Virtuoso, Cygwin.

RELEVENT COURSEWORK: 1) ASIC CMOS Design 2) Linear System Theory 3) Semiconductor Devices 4) Advanced Logic Design

5) Computer Architecture 6) Digital System Design and Synthesis 7) SoC Design and Verification with System Verilog.

WORK EXPERIENCE:

Jr. Verification Engineer, Scalable Systems Research Labs Inc. (Pacifica, CA) (March 2017-Present)

SPI Controller Core Verification:

Responsible for developing the Test Bench Environment consisting of Generator, BFM, Monitor and Coverage modules.

Studied and understood the SPI Protocol and the working of implemented SPI Controller Core design modules.

Contribute in developing Test Plan and implementation of various test cases using System Verilog.

Performed emulations for regression testing and debugged different verification errors using Questa Sim Tool.

Test Engineer, Infostretch Corporation (Santa Clara, CA) (Mar 2016-Aug 2016)

Intel Skylake / Broadwell Project and Intel Cherrytrail / Clovertrail / Baytrail Projects:

Tested Intel Skylake / Broadwell Chips on the Pre-Market Devices (2-in-1s and All-in-Ones) & Zenfone (Asus) device.

Used Intel Graphics Performance Analyzer and FRAPS tools to test the Frames Per Second (FPS) for Advanced Apps.

Analyzed and monitored the power and performance parameters for the device using System Panel application.

Maintained the excel sheet for performance and collected the error logs for crashing apps from Android Studio.

ACADEMIC PROJECTS:

AXI VIP Development using System Verilog (Tool Used: Questa Sim) (Fall 2016)

Developed AXI VIP architecture with VIP components for AXI 3.0 protocol.

The architecture supported various features like burst type, burst size, protection, out of order, overlapping, aligned, etc.

Implemented test bench components like BFM (Bus Functional Model), Generator, Monitor and Coverage models.

Developed various Scenarios and Test cases for the Validation of the above features.

Ethernet Packet Loopback design verification using System Verilog (Tool Used: Questa Sim) (Spring 2016)

Design checks the incoming Ethernet packets at the receive interface for CRC, SoF, Data length errors, etc.

Packet is looped back on Transmit interface if it is good, else it is dropped.

As the part of design verification, Test Bench which generates all types of Ethernet packets was developed.

Ref. model for self-checking with Verification closure using Functional Coverage & Code Coverage as closing criteria.

Designed Altera Nios-II Processor (Tool Used: Altera Quartus II, Synopsys VCS) (Fall 2015)

Designed five individual modules for Fetch, Decode, Execute, Memory access and Write Back.

Design consisted of components like Control unit, Program counter and an ALU for executing the instructions.

Two types of word formats were handled by the designed processor such as I-type and R-type.

The designed process in the project computed a Dot Product of the two vectors.

Designed and Synthesized RMS value calculator for series of numbers (Tool Used: NC Verilog, Synopsys VCS) (Spring 2015)

Implemented, designed, simulated and synthesized RMS value calculator.

Divide and Square Root were implemented in the form of algorithms.

The design was pipelined for more than 60 stages to achieve timing constraints.

Push pull flags had been employed at input and output interfaces to avoid FIFO overrun and underrun.

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