| Distance: | Resume alert | Resumes 131 - 140 of 821 |
Physical Design Trainee
Bangalore, Karnataka, India
... Professional Traits Arduino ICC Innovus Perl Physical design VLSI C Synthesis STA Virtuoso Genus Tempus PNR verilog Python Seeking a quality environment where my knowledge can be shared and will have impact on company‘s growth, at the same time ... - 2019 Aug 08
... Professional Traits Arduino ICC Innovus Perl Physical design VLSI C Synthesis STA Virtuoso Genus Tempus PNR verilog Python Seeking a quality environment where my knowledge can be shared and will have impact on company‘s growth, at the same time ... - 2019 Aug 08
Design Power
Vasant Nagar, Karnataka, India
... Basic knowledge of CMOS and VLSI fundamentals. Good analytical, design and problem solving skills. Worked on Cadence Virtuoso with UMC 180nm technology. Academic Details: Year Qualification Board/University Marks in % / CGPA 2019 M.Tech VIT ... - 2019 Aug 08
... Basic knowledge of CMOS and VLSI fundamentals. Good analytical, design and problem solving skills. Worked on Cadence Virtuoso with UMC 180nm technology. Academic Details: Year Qualification Board/University Marks in % / CGPA 2019 M.Tech VIT ... - 2019 Aug 08
Design Project
Koramangala, Karnataka, India
J Shyam Sai Pavan kumar MTech in VLSI & ES PESIT - BSC Electronic City, Bangalore- 560100 Email: *******************@*****.*** Mobile : +9 1 - 776******* Objective Seeking a position with an organization where I can contribute my skills for ... - 2019 Aug 07
J Shyam Sai Pavan kumar MTech in VLSI & ES PESIT - BSC Electronic City, Bangalore- 560100 Email: *******************@*****.*** Mobile : +9 1 - 776******* Objective Seeking a position with an organization where I can contribute my skills for ... - 2019 Aug 07
Test Cases Engineering
Bangalore, Karnataka, India
... ,VIVADO Questa Sim, HFSS Education July 2018 Master of Technology at Amrita School of Engineering, Coimbatore Major: VLSI Design Thesis: “Hardware Trojan detection using Deep Learning technique.” Gpa: 8.77 July 2015 Bachelor of Technology at ... - 2019 Jul 28
... ,VIVADO Questa Sim, HFSS Education July 2018 Master of Technology at Amrita School of Engineering, Coimbatore Major: VLSI Design Thesis: “Hardware Trojan detection using Deep Learning technique.” Gpa: 8.77 July 2015 Bachelor of Technology at ... - 2019 Jul 28
Design Engineering
Vasant Nagar, Karnataka, India
... Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using industry standard EDA tools for the front-end design and verification VLSI Domain Skills HDL : Verilog HVL : ... - 2019 Jul 12
... Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using industry standard EDA tools for the front-end design and verification VLSI Domain Skills HDL : Verilog HVL : ... - 2019 Jul 12
Verilog, System Verilog, UVM, SOC Verification, ASIC Verification
Vasant Nagar, Karnataka, India
... September 2016 – December 2017 Done VLSI Design and Verification course at Maven silicon, Bangalore. June 2017 – January 2018 Expertise Skills: • Experienced in writing Test benches in System Verilog / UVM. • Developed a test plan and setup the test ... - 2019 Jul 08
... September 2016 – December 2017 Done VLSI Design and Verification course at Maven silicon, Bangalore. June 2017 – January 2018 Expertise Skills: • Experienced in writing Test benches in System Verilog / UVM. • Developed a test plan and setup the test ... - 2019 Jul 08
Engineer Design
Karnataka, India
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17
Project Security
Vasant Nagar, Karnataka, India
... ACADEMIC PROJECTS: PROJECT-1: Title of the project : Development of Efficient VLSI architecture for speech processing in mobile communication. Duration : 6 months Team size : 4 Description: Design of specific architecture for a given application is ... - 2019 May 08
... ACADEMIC PROJECTS: PROJECT-1: Title of the project : Development of Efficient VLSI architecture for speech processing in mobile communication. Duration : 6 months Team size : 4 Description: Design of specific architecture for a given application is ... - 2019 May 08
Engineering Design
Vasant Nagar, Karnataka, India
... VLSI Domain Skills HDL : Verilog HVL : SystemVerilog Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology : UVM Protocols : AXI, AHB, UART, I2C, SPI EDA Tool : Questasim and ISE Domain : ASIC ... - 2019 Apr 19
... VLSI Domain Skills HDL : Verilog HVL : SystemVerilog Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology : UVM Protocols : AXI, AHB, UART, I2C, SPI EDA Tool : Questasim and ISE Domain : ASIC ... - 2019 Apr 19
Engineering Project
Pulikeshi Nagar, Karnataka, India
... WORKSHOPS AND CONFERENCES •QSOCs TECHNOLOGIES PVT.LTD •BANGALORE • 31st MARCH, 2018 Attended a one day internship on VLSI •HKBK COLLEGE OF ENGINEERING, BANGALORE • FEBRUARY, 2018 Attended a workshop on “Arduino” for student development program ... - 2019 Apr 11
... WORKSHOPS AND CONFERENCES •QSOCs TECHNOLOGIES PVT.LTD •BANGALORE • 31st MARCH, 2018 Attended a one day internship on VLSI •HKBK COLLEGE OF ENGINEERING, BANGALORE • FEBRUARY, 2018 Attended a workshop on “Arduino” for student development program ... - 2019 Apr 11