Test Cases Engineering

Reshma K

Personal Data

Place and Date of Birth: Thallasery, Kerala 15 May 1994

Address: Kamala Nivas, Kariyad South, Kannur, Kerala, India Phone: 854-***-****, 809-***-****

email: *.********@*****.***

INTERNSHIP DETAILS

Current Intern at Intel Technology Pvt.Ltd

Jan 2018 - Jul 2018 SOC Level functional verification of USB 2.0 Based on the verification objectives of USB 2.0, test cases are developed to check the functionalities like bulk data transfer, memory, register access, data transfer in different power states, etc. These test cases are written in C language and are simulated using iRunner tool. Test cases are made to pass in regression and verified the functionalities of USB2.0.

Projects

Thesis Hardware Trojan detection using Deep Learning technique Tools Used Synopsys Tetra Max

Languages Used Verilog, Python

Based on controllability and transition probability analysis, trojan nodes are isolated using deep learning algorithm and the technique is validated on ISCAS’85 benchmark circuits.Published at International Conference on Soft Computing and Signal Processing. Course Project A New Approach to Reduce Leakage Power for Low Power Design Tools Used Cadence Virtuoso

Stacked keeper with body bias (SK-BB) design used to reduce static leakage reduction. Course Project Fault Analysis-Based Logic Encryption Tools Used VIVADO

Languages Used Verilog

Combinational circuit is encrypted by inserting a key gate in high fault impact value nodes.

Thesis Narrow Band Micro-Strip Patch Antenna at Terahertz Frequency Tools Used HFSS

Simulating a rectangular microstrip patch antenna at THz frequencies using HFSS (high frequency structural simulator.

Mini Project RFID based supermarket trolley and display system Technical Skills

Programming Language: Verilog, System Verilog, C Programming, Tools Used: CADENCE (Virtuoso, nclaunch, Encounter), SYNOPSYS (Design Compiler, Prime Time, TetraMax, Custom designer),VIVADO Questa Sim, HFSS

Education

July 2018 Master of Technology at Amrita School of Engineering, Coimbatore Major: VLSI Design

Thesis: “Hardware Trojan detection using Deep Learning technique.” Gpa: 8.77

July 2015 Bachelor of Technology at College Of Engineering, Thalassery Branch: Electronics and Communication Engineering

Thesis: “Narrow Band Micro-Strip Patch Antenna at Terahertz Frequency.” Aggregate: 70.67%

Fall 2011 12th Standard at Ramavilasam Higher Secondary School, Thalassery, Kerala Stream: Science (Maths, Physics, Biology)

Aggregate: 83.75%

Fall 2009 10th Standard at Ramakrishna High School, Thalassery, Kerala Aggregate: 98%

AWARDS & ACHIEVEMENTS

Rajya Puraskar Guide Award.

Participated in State Level ball badminton tournament. Second place in 1 year M-Tech, VLSI Design degree examination. Won prizes in district level social science-work experience fair. Sub district level winner in athletics (800m, 400m, 4*400m, 4*100m, 5km walk). Won prizes in dancing and recitation.

EXTRA CURRICULAR ACTIVITES

Participated in AISec 2017 Workshop: Modern Artificial Intelligence (AI) and Natural Lan- guage Processing (NLP) Techniques for Cyber security. Volunteer of College Technical Fest ‘Agnitus 2K14’. Member of National Service Scheme.

Member of Scouts & Guides.

DECLARATION

Hereby I assure that the above mentioned information is true to the best of my knowledge. Reshma K

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