| Resume alert | Resumes 161 - 170 of 929 |
Verilog, System Verilog, UVM, SOC Verification, ASIC Verification
Vasant Nagar, Karnataka, India
... September 2016 – December 2017 Done VLSI Design and Verification course at Maven silicon, Bangalore. June 2017 – January 2018 Expertise Skills: • Experienced in writing Test benches in System Verilog / UVM. • Developed a test plan and setup the test ... - 2019 Jul 08
... September 2016 – December 2017 Done VLSI Design and Verification course at Maven silicon, Bangalore. June 2017 – January 2018 Expertise Skills: • Experienced in writing Test benches in System Verilog / UVM. • Developed a test plan and setup the test ... - 2019 Jul 08
Engineer Design
Karnataka, India
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17
... VLSI Good understanding of the ASIC and FPGA design flow Extensive experience in writing RTL models using Verilog HDL. Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies TOOLS ... - 2019 Jun 17
Project Security
Vasant Nagar, Karnataka, India
... ACADEMIC PROJECTS: PROJECT-1: Title of the project : Development of Efficient VLSI architecture for speech processing in mobile communication. Duration : 6 months Team size : 4 Description: Design of specific architecture for a given application is ... - 2019 May 08
... ACADEMIC PROJECTS: PROJECT-1: Title of the project : Development of Efficient VLSI architecture for speech processing in mobile communication. Duration : 6 months Team size : 4 Description: Design of specific architecture for a given application is ... - 2019 May 08
Engineering Design
Vasant Nagar, Karnataka, India
... VLSI Domain Skills HDL : Verilog HVL : SystemVerilog Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology : UVM Protocols : AXI, AHB, UART, I2C, SPI EDA Tool : Questasim and ISE Domain : ASIC ... - 2019 Apr 19
... VLSI Domain Skills HDL : Verilog HVL : SystemVerilog Verification Methodologies: Coverage Driven Verification Assertion Based Verification - SVA TB Methodology : UVM Protocols : AXI, AHB, UART, I2C, SPI EDA Tool : Questasim and ISE Domain : ASIC ... - 2019 Apr 19
Engineering Project
Pulikeshi Nagar, Karnataka, India
... WORKSHOPS AND CONFERENCES •QSOCs TECHNOLOGIES PVT.LTD •BANGALORE • 31st MARCH, 2018 Attended a one day internship on VLSI •HKBK COLLEGE OF ENGINEERING, BANGALORE • FEBRUARY, 2018 Attended a workshop on “Arduino” for student development program ... - 2019 Apr 11
... WORKSHOPS AND CONFERENCES •QSOCs TECHNOLOGIES PVT.LTD •BANGALORE • 31st MARCH, 2018 Attended a one day internship on VLSI •HKBK COLLEGE OF ENGINEERING, BANGALORE • FEBRUARY, 2018 Attended a workshop on “Arduino” for student development program ... - 2019 Apr 11
Design Engineering
Vasant Nagar, Karnataka, India
... Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using industry standard EDA tools for the front-end design and verification VLSI Domain Skills HDL : Verilog HVL : ... - 2019 Apr 10
... Good experience in writing Test benches using SystemVerilog and UVM Very good knowledge in verification methodologies Experience in using industry standard EDA tools for the front-end design and verification VLSI Domain Skills HDL : Verilog HVL : ... - 2019 Apr 10
Design Verification Engineer
Vasant Nagar, Karnataka, India
... Xavier’s High School, Jagdalpur Dicipline: ICSE Percentage: 60% Year: 2011 Professional Qualification: Advanced VLSI Design and Verification course Maven Silicon VLSI Design and Training Center, Bengaluru. JULY-2018 to JAN-2019. VLSI Domain Skills: ... - 2019 Apr 05
... Xavier’s High School, Jagdalpur Dicipline: ICSE Percentage: 60% Year: 2011 Professional Qualification: Advanced VLSI Design and Verification course Maven Silicon VLSI Design and Training Center, Bengaluru. JULY-2018 to JAN-2019. VLSI Domain Skills: ... - 2019 Apr 05
Test Cases
Vasant Nagar, Karnataka, India
... HDL: Verilog Tool: Questa sim 10.4e Education qualification: Qualification/ course Specialization Name of the college/institute Year of study Grade acquired VLSI front-end Front-end design and verification VLSIguru institute 2018 Completed success ... - 2019 Apr 04
... HDL: Verilog Tool: Questa sim 10.4e Education qualification: Qualification/ course Specialization Name of the college/institute Year of study Grade acquired VLSI front-end Front-end design and verification VLSIguru institute 2018 Completed success ... - 2019 Apr 04
Training Design
Bangalore, Karnataka, India
... CORECOMPATENCY: VLSI CORE • Good Knowledge on VLSI concepts and Tool based experience on Physical Design in IC Compiler. Understanding knowledge in RTL coding (Verilog and VHDL) with FPGA Prototype. • Exposure to EDA Tools: Synopsis IC-Compiler. • ... - 2019 Mar 05
... CORECOMPATENCY: VLSI CORE • Good Knowledge on VLSI concepts and Tool based experience on Physical Design in IC Compiler. Understanding knowledge in RTL coding (Verilog and VHDL) with FPGA Prototype. • Exposure to EDA Tools: Synopsis IC-Compiler. • ... - 2019 Mar 05
Engineer Project
Bangalore, Karnataka, India
... TRAINING DETAIL Did VLSI training course at Vector India Institute, Hyderabad from 15 October, 2012 to 15 March, 2013 TECHNICAL SKILLS Protocol Knowledge: Ethernet, AHB, APB, DDR 3 HDL & HVL: VHDL, Verilog, System Verilog FPGA: Xilinx ISE 12.3i ... - 2019 Feb 18
... TRAINING DETAIL Did VLSI training course at Vector India Institute, Hyderabad from 15 October, 2012 to 15 March, 2013 TECHNICAL SKILLS Protocol Knowledge: Ethernet, AHB, APB, DDR 3 HDL & HVL: VHDL, Verilog, System Verilog FPGA: Xilinx ISE 12.3i ... - 2019 Feb 18