Design Power

Viraj Vijay Bhusari Mobile No: 887*******

Email Id: ********@*****.***

Objective:

To utilize my Engineering knowledge in efficient service of organization to secure challenging position and contribute for organizational and social cause. Core Competency:

Familiar with ASIC design flow.

Technical exposure on floor planning, place and route, clock tree synthesis, timing analysis, DRC/LVS.

Worked on 90nm technology.

Hands on experience on Synopsys EDA tool.

Basic knowledge of CMOS and VLSI fundamentals.

Good analytical, design and problem solving skills.

Worked on Cadence Virtuoso with UMC 180nm technology. Academic Details:

Year Qualification Board/University Marks in % /

CGPA

2019 M.Tech VIT University 8.28

2016 B.E Dr.B.A.M.U 7.3

2012 HSC MAHARASHTRA 78.33%

2010 SSC MAHARASHTRA 85.04%

Technical skills:

Programming Language Verilog HDL, PERL(beginner level), System Verilog(beginner level) EDA TOOLS Synopsys EDA tools:

IC compiler

Prime time

Cadence EDA tool:

Cadence virtuoso

Mentor graphics:

Modelsim(HDL simulation)

FPGA Synthesis Tool:

Quartus altera

Xilinx Vivado Design Suite.

Master’s Thesis:

Design of Low Power Continuous-Time Delta-Sigma Modulator with Body Driven Comparator

Tools and Technology Used: Cadence Virtuoso and 180nm Technology. This project is about reducing power in delta-sigma modulator using body driven comparator and increasing SNR by reducing bandwidth of system.

M.Tech Projects:

Sr

no.

Project Title Technology/

specification

Role/responsibility

1 Low-Leakage

Asymmetric 7T SRAM

90nm Reducing leakage power by using stacking effect and by use of multi threshold transistors.

2 Clock-less Design for

Reconfigurable

Floating Point

Multiplier

- Making RTL code for floating point multiplier

with better performance in terms of area and

power.

3 Design and Analysis of

Radiation Hardened

Latches for Nanoscale

CMOS

90nm Designing and analyzing various schemes for

making latch radiation hardened by using

Schmitt trigger for increasing critical charge on

sensitive node.

4 Round Robin Arbiter 90nm

200MHz

RTL coding, Floor Plan, Placement, Timing

Optimizing, CTS, Routing, Timing analysis.

Area of Interest:

ASIC Design

Digital IC Design

Analog IC Design

Verification

DFT

Personal details:

- Name: Viraj V. Bhusari

- Fathers name: Vijay V. Bhusari

- Gender: Male

- Date of Birth: 18/08/1994

- Languages Known: English, Hindi, Marathi.

- Permanent Address: Flat no.2 Shrimangal Appartment, near chumbak ghar, Ranpise Nagar Akola, Maharashtra- 444001.

Declaration:

I do hereby declare that the above given statements are true and correct to the best of my knowledge.

Date: 27/05/2019 Bhusari Viraj Vijay

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