J Shyam Sai Pavan kumar

MTech in VLSI & ES

PESIT - BSC

Electronic City, Bangalore- 560100

Email: ac90lh@r.postjobfree.com

Mobile : +9 1 - 776*******

Objective

Seeking a position with an organization where I can contribute my skills for organization’s success and synchronize with new technology while being resourceful, innovative and flexible. Skill Set

EDA Tools : Cadence Virtuoso, Innovus, NCLaunch, encounter, Tempus and Vivado, Cadence Orcad, ICC2

Hardware Description Languages : Verilog.

Software Skills : C-Programming.

Platforms : Linux, Windows.

Hardware Systems : NXP ARM Cortex M3 (for Embedded Applications), Basys3 FPGA Board (Processor Based System

Design)

Technical Skills : Physical Design, Analog & Mixed Signal Circuit Design, STA and PCB Design.

Hands on

Analysis of different types of Inverters and Amplifiers in Cadence Virtuoso during M.Tech

Digital Physical design Implementation of Block level for various designs in Innovus. Academic Profile

Degree Board / University Year CGPA / Percentage

MTech [VLSI &

Embedded Systems]

[ PES]VTU 2017 - 2019 7.9

B.E [ECE] [ SSEC]VTU 2013 - 2017 65.33 %

Internship

Organization: PESU RESEARCH FOUNDATION

Description: Exploring of MEMS (Micro-Electro-Mechanical-Systems) design for next generation Sensor. By using tools ANSYS and COMSOL. The analysis depends on geometry, processing and martial. For the sample purpose the modelling of MEMS Accelerometer using COMSOL tool with Low power and high Sensitivity. For this model Analog readout circuitry has been model using MATLAB and then verified.

Projects

MTech

1) Title: Physical Design implementation of Leon Processor The Leon design is block level design with 35K instances, 4 memories and 1200 I/O pins. The technology library used is 45nm using 9 routing layers. Performed all sanity checks, CTS, generated all power and timing reports.

B.E Project

2) Title: Smart Dustbin

The Smart Dustbin is a cheap, easy to use solution for a segregation system at Public Places such as Railway stations, Shopping malls, Historical places etc. The processor used is ATmega328p. It is designed to sort and refuse into metallic waste, wet waste and dry waste. It was selected by IEDC Council Best innovation project of 2016-2017 ECE branch. Achievements

The project SMART DUSTBIN was selected by IEDC Council as Best innovation project of 2016-2017 ECE branch.

Secured 2

nd place in presenting paper on “NANO TECHNOLOGY” in National Level Technical Symposium (26/09/2013)

Presented paper on SMART DUSTBIN in 3

rd

INTERNATIONAL CONFERENCE ON

APPLIED SCIENCE ENGINEERING AND TECHNOLOGY (ICSET-17)

Organized and Donated “Blood Donation camp” in our college. PERSONAL PROFILE

Father Name : J Prabhakar Rao

Gender : Male

Date of birth : 22-11-1995

Blood group : A +ve

Languages known : English, Hindi, Kannada, Telugu. Hobbies : Writing Stories, Playing mobile games, Cricket and Badminton.

(J Shyam Sai Pavan Kumar)

SIGNATURE