| Distance: | Resume alert | Resumes 111 - 120 of 821 |
Graphic Designer Project
Vasant Nagar, Karnataka, India
... C, C++, Verilog HDL-Xilinx, Matlab, Embedded C- Keil, ARM Cortex-M3, VLSI-Cadence Microprocessor -8086 and MicroController-MSP430 PROJECT AND INTERNSHIP: Mini project in Verilog HDL- A digital alarm clock displays time in the LCD display format. ... - 2020 Feb 16
... C, C++, Verilog HDL-Xilinx, Matlab, Embedded C- Keil, ARM Cortex-M3, VLSI-Cadence Microprocessor -8086 and MicroController-MSP430 PROJECT AND INTERNSHIP: Mini project in Verilog HDL- A digital alarm clock displays time in the LCD display format. ... - 2020 Feb 16
Power System
Vasant Nagar, Karnataka, India
... Completed internship on “Study and Testing of Electrical Equipments” in RT Division, Kptcl, Ballari, from Aug 2016 to Nov 2016 CERTIFICATES VLSI DESIGN AND VERIFICATION COURSE TRUEVLSI Learning Centre, Bengaluru ACADEMIC DETAILS 2017 M.Tech/M.E. ... - 2020 Feb 06
... Completed internship on “Study and Testing of Electrical Equipments” in RT Division, Kptcl, Ballari, from Aug 2016 to Nov 2016 CERTIFICATES VLSI DESIGN AND VERIFICATION COURSE TRUEVLSI Learning Centre, Bengaluru ACADEMIC DETAILS 2017 M.Tech/M.E. ... - 2020 Feb 06
Inplant Training Engineering
Vasant Nagar, Karnataka, India
... Road and Transport Technology RESEARCH Efficient FIR Filter Implementation using Multiple Constant Multiplication Platform : VLSI Design Description : Resource minimization problem is identified in the scheduling of adder-tree operation for the MCM ... - 2020 Feb 05
... Road and Transport Technology RESEARCH Efficient FIR Filter Implementation using Multiple Constant Multiplication Platform : VLSI Design Description : Resource minimization problem is identified in the scheduling of adder-tree operation for the MCM ... - 2020 Feb 05
Design Engineer
Vasant Nagar, Karnataka, India
... + Indian Institute of Information Technology Gwalior, Madhya Pradesh M.Tech, VLSI DESIGN 2017–2019 CGPA:6.63 + Govt. Indira Gandhi Engineering College,Sagar Sagar,Madhya Pradesh B.Tech, Electronics & Communication 2009–2013 66% + Miss Hill School ... - 2020 Feb 05
... + Indian Institute of Information Technology Gwalior, Madhya Pradesh M.Tech, VLSI DESIGN 2017–2019 CGPA:6.63 + Govt. Indira Gandhi Engineering College,Sagar Sagar,Madhya Pradesh B.Tech, Electronics & Communication 2009–2013 66% + Miss Hill School ... - 2020 Feb 05
Design Project
Bangalore, Karnataka, India
... Advanced VLSI Design and Verification Course in Maven silicon, VLSI Design and Training Center, Bangalore Course Discipline University/Board Year of pass Aggregate B. Tech ECE Vignan’s University 2019 83.25% Intermediate M.P.C BOI 2015 94.6% S.S.C ... - 2020 Jan 08
... Advanced VLSI Design and Verification Course in Maven silicon, VLSI Design and Training Center, Bangalore Course Discipline University/Board Year of pass Aggregate B. Tech ECE Vignan’s University 2019 83.25% Intermediate M.P.C BOI 2015 94.6% S.S.C ... - 2020 Jan 08
C,C++,Verilog
Bangalore, Karnataka, India
... PROGRAMMING LANGUAGE AND UTILITIES Verilog Xilinx 14.7 C and C++ Turbo C Pcb designing Protel Advance 2.7.1 SKILLS Knowledge of Cmos fundamentals,fabrication Vlsi basics Digital and analog electronics Memories communication basics Static timing ... - 2019 Nov 24
... PROGRAMMING LANGUAGE AND UTILITIES Verilog Xilinx 14.7 C and C++ Turbo C Pcb designing Protel Advance 2.7.1 SKILLS Knowledge of Cmos fundamentals,fabrication Vlsi basics Digital and analog electronics Memories communication basics Static timing ... - 2019 Nov 24
Engineering Project
Vasant Nagar, Karnataka, India
... ACADEMIC QUALIFICATIONS M-TECH Visvesvaraya Technological University (2017-2019) VLSI and Embedded System, secured 8.0 CGPA Bangalore Institute of Technology, Bangalore B.E Visvesvaraya Technological University (2013-2017) Electrical and Electronics ... - 2019 Nov 13
... ACADEMIC QUALIFICATIONS M-TECH Visvesvaraya Technological University (2017-2019) VLSI and Embedded System, secured 8.0 CGPA Bangalore Institute of Technology, Bangalore B.E Visvesvaraya Technological University (2013-2017) Electrical and Electronics ... - 2019 Nov 13
Engineer Engineering
Vasant Nagar, Karnataka, India
... Mother’s Name : M V Revathi Nationality : Indian COURSES Advanced VLSI Design and Verification course Maven Silicon VLSI Design and Verification Training Center, Bangalore JULY 2018 -MAR 2019 PROJECTS [1].PANTHERBOTICS - Final year BE Project. ... - 2019 Oct 25
... Mother’s Name : M V Revathi Nationality : Indian COURSES Advanced VLSI Design and Verification course Maven Silicon VLSI Design and Verification Training Center, Bangalore JULY 2018 -MAR 2019 PROJECTS [1].PANTHERBOTICS - Final year BE Project. ... - 2019 Oct 25
Engineering Design
Bangalore, Karnataka, India
... • VLSI Project :-Radiation hardening by design 12T SRAM for aerospace application using nanoscale cmos technology. Internship Experience • Worked as an intern in Global technologies (Embedded system and IOT) from 5th July 2018 to 5th Aug 2018. ... - 2019 Oct 25
... • VLSI Project :-Radiation hardening by design 12T SRAM for aerospace application using nanoscale cmos technology. Internship Experience • Worked as an intern in Global technologies (Embedded system and IOT) from 5th July 2018 to 5th Aug 2018. ... - 2019 Oct 25
Sales Engineering
Vasant Nagar, Karnataka, India
... PROJECTS “Design of high-speed low power VLSI adder with error tolerance”. HOBBIES Dancing and cooking. PERSONAL DETAILS Father’s Name : Mahesh Chandra Mother’s Name : Ushalatha Date of Birth : 23rd May 1994 Languages known : English, Hindi, Kannada ... - 2019 Oct 17
... PROJECTS “Design of high-speed low power VLSI adder with error tolerance”. HOBBIES Dancing and cooking. PERSONAL DETAILS Father’s Name : Mahesh Chandra Mother’s Name : Ushalatha Date of Birth : 23rd May 1994 Languages known : English, Hindi, Kannada ... - 2019 Oct 17